Electrical Property of Semiconductor

1.1.4.1 Introduction—Dopants and Impurities in Silicon

Semiconductors are solid materials that have electrical conductivities in between those of conductors and those of insulators. The physical reason causing a material to behave as a conductor, semiconductor, or insulator lies in the availability, or lack thereof, of free current carriers in the material. Semiconductors are characterized by the narrow bandgap between the valence bands, occupied by electrons, and the conduction band, in which electrons move freely according to applied electrical fields. Intrinsic (i.e., pure) semiconductors act as insulators at room temperatures, but their behavior changes dramatically with temperature, and, more to the point, with small impurities present in the crystal. Very small amounts of electrically active impurities can totally alter the electrical properties of semiconductors such as silicon. This is because the electrically active impurities either easily donate valence electrons (donors) or accept them, creating holes (acceptors). These electrons or holes are free (i.e., not bound to individual atoms). Their movement due to applied electrical fields carries electrical currents, giving rise to the term charge carriers used to denote them.

The electrical properties of semiconductor materials such as single-crystal silicon are thus defined by the impurity concentrations present in the silicon lattice. Impurities are introduced into the starting materials during crystal growth and modified during device processing by additional doping of the silicon material with electrically active impurities. In intentional doping of silicon, impurity atoms from group III (acceptors) and group V (donors) are used. The dopants used in crystal pulling, and the conductivities reached with specific impurity concentrations, are described in more detail in Sections 3.1 and 3.3Section 3.1Section 3.3, Dopants and impurities in silicon crystals.

Manipulation of the electrical properties in the structures created during MEMS device manufacturing follows practices established in semiconductor device manufacturing. Techniques used include both very traditional methods, such as deep diffusions of dopants, which have been abandoned in mainstream semiconductor processes, and current standard techniques such as ion implantation and epitaxial deposition. While semiconductor-grade starting materials are largely free of other electrically active impurities, the incorporation of unintentional contamination into silicon during processing can have significant effects on the electrical properties of the manufactured devices.

Unintentional doping of silicon includes the introduction of unwanted donors or acceptors to the crystal lattice from the processing environment. These impurities can be either group III/V-type atoms misplaced, or other contaminants, such as some transition metals.

The generation of electrically active donors also takes place within the single-crystal CZ silicon itself, without the introduction of additional impurities. CZ silicon always includes a few parts per million atoms of interstitial oxygen atoms, originating from the quartz crucible used to hold the melt during crystal pulling (see also Chapter 3). At certain temperatures, ranging from 400°C to 550°C, these interstitial atoms create conglomerates of several oxygen atoms within the lattice. Such silicon–oxygen microclusters are known as thermal donors (TDs), as they donate free electrons to the conduction band, influencing the electrical properties accordingly [22,23]. The concentration is, however, usually below 10¹⁵×cm⁻³, and thus has only very marginal effects on other than high-resistivity silicon. These donors are not stable at temperatures above 600°C, and even for applications requiring high-resistivity silicon, their effect can be suppressed by quick cooling down over the generation temperature range. This method is called thermal donor anneal (TDA), and while it is effective, it does not prevent the generation of new TD if temperatures in the critical range are used later in the device processing. For further details, see Section 3.6.

The use of semiconductors is based on the fact that the charge carrier concentrations are also influenced by any electric fields that are present. This can take place intentionally, as, for example, in transistors, but also due to electric fields generated by surface effects such as charging. These effects are more pronounced in high-resistivity silicon, but they bear consideration in general.

In the vast majority of cases, the electronics required for the realization of a MEMS-based sensor consist of the basic building blocks of semiconductor electronics used since the birth of the silicon-based semiconductor industry and described in the basic handbooks of the industry, such as Sze [24]. In MEMS applications requiring very high resistivity, in fields such as RF and optical, special considerations apply. The very high resistivity materials used are obviously strongly affected by even the smallest concentrations of unintended charge carriers. These unintended charge carriers can be introduced into the material by methods such as TD generation (described earlier), oxidation, and contamination of the surface if the donors/acceptors are not subsequently evaporated. In very high resistivity silicon, these effects can be severe, in some cases even leading to type reversal.

1.1.4.2 Piezoresistive Effect in Silicon

1.1.4.2.4 Strain Effect on Resistivity

In metals the conduction/valence bands are partially filled with charge carriers, and small changes in band shape do not affect most of the carriers. In semiconductors the shape and dimension of the bandgap has a much larger effect, and shifts in energy bands due to applied stress affect the mobility of charge carriers. The result is resistivity change due to applied stress and gauge factors up to two magnitudes larger than those observed in metals. Because the relative change in resistivity is proportional to strain, it can be written as:

(1.5)$\frac{\mathrm{\Delta }\rho }{\rho }=Y{\pi }_L{\epsilon }_L$

For strained anisotropic material, the resistivity is thus no longer scalar and is described through tensor mathematics, similar to the mathematics described earlier for stresses in anisotropic material. Thus, the dependence of the current density J on the electric field E is denoted as:

(1.6)$\left[\begin{array}{c}{E}_x\\ E_y\\ E_z\end{array}\right]=\left[\begin{array}{ccc}{\rho }_{xx}& {\rho }_{xy}& {\rho }_{xz}\\ {\rho }_{xy}& {\rho }_{yy}& {\rho }_{yz}\\ {\rho }_{xz}& {\rho }_{zy}& {\rho }_{zz}\end{array}\right]\left[\begin{array}{c}{J}_x\\ J_y\\ J_z\end{array}\right]$

Details of the tensor mathematics explaining the anisotropic resistivity are described in, for example, Thomsen [26].

In typical applications the MEMS devices are constructed in such a way that the current in the piezoresistors is either parallel or perpendicular to the direction of the stress. Also, the vast majority of applications are made on (100) silicon wafer substrates, with the substrate oriented in such a way that the resistors are aligned on the [110] direction on p-type and the [100] direction in n-type, as depicted in Figure 1.13. These directions yield the maximum positive and negative piezo coefficients (i.e., the maximum relative resistivity change for a given applied force).

Figure 1.13. Typical piezoresistor alignments used on MEMS-standard (100) silicon wafers, aligned to utilize maximum piezo coefficients for rectangular membranes of the type used in pressure sensors. (a) P-type silicon, Dicing along <110>, (b) P-type silicon, Dicing along <100>, (c) N-type silicon, Dicing along <100>.

For a system in which the coordinates are chosen to coincide with the crystallographic axes, the relationship between the stress tensor and the anisotropic change in resistivity simplifies due to crystallographic symmetries of silicon, and can be defined as:

(1.7)$\frac{1}{\rho }·\left[\begin{array}{c}\partial {\rho }_{11}\\ \partial {\rho }_{22}\\ \partial {\rho }_{33}\\ \partial {\rho }_{23}\\ \partial {\rho }_{13}\\ \partial {\rho }_{12}\end{array}\right]=\left[\begin{array}{cccccc}{\mathrm{\Pi }}_{11}& {\mathrm{\Pi }}_{12}& {\mathrm{\Pi }}_{12}& 0& 0& 0\\ {\mathrm{\Pi }}_{12}& {\mathrm{\Pi }}_{11}& {\mathrm{\Pi }}_{12}& 0& 0& 0\\ {\mathrm{\Pi }}_{12}& {\mathrm{\Pi }}_{12}& {\mathrm{\Pi }}_{11}& 0& 0& 0\\ 0& 0& 0& {\mathrm{\Pi }}_{44}& 0& 0\\ 0& 0& 0& 0& {\mathrm{\Pi }}_{44}& 0\\ 0& 0& 0& 0& 0& {\mathrm{\Pi }}_{44}\end{array}\right]\left[\begin{array}{c}\partial {\sigma }_{11}\\ \partial {\sigma }_{22}\\ \partial {\sigma }_{33}\\ \partial {\sigma }_{23}\\ \partial {\sigma }_{13}\\ \partial {\sigma }_{12}\end{array}\right]$

where Π₁₁, Π₁₂ and Π₄₄ represent three independent piezo coefficients, listed in Table 1.2.

Table 1.2. Independent Piezo Coefficients for Crystalline Bulk Silicon [25,27]

10−11 1/Pa	n-Si ND=4×1014 [25]	p-Si NA 2×1015 [25]	p-Si NA 1×1018 [27]	p-Si NA 1×1019 [27]
Π11	−102	+6,6
Π12	+53	−1,1
Π44	−14	+138	+103	+81

In most applications the change in resistivity is limited to stresses parallel and perpendicular to the resistive path. In such cases, the situation is greatly simplified [28]. The tensor element becomes a scalar equation, and can be written as:

(1.8)$\frac{\partial \rho }{\rho }={\pi }_{\mathrm{l}}{\sigma }_{\mathrm{l}}+{\pi }_{\mathrm{t}}{\sigma }_{\mathrm{t}}$

where the common notions of longitudinal piezo coefficient π_l and transversal piezo coefficient π_t are used. As an example of a common situation, let us consider the case of a p-type piezoresistor constructed to utilize the maximum piezo sensitivity as described in Figure 1.13(a). For such a resistor, which is uniaxially stressed and lying in the (110) direction, the shear strain is zero and the longitudinal piezo coefficient is simplified to:

(1.9)${\pi }_{\mathrm{l}}=\frac{1}{2}[{\pi }_{11}+{\pi }_{12}+{\pi }_{44}]$

The corresponding transversal piezo coefficient then becomes

(1.10)${\pi }_{\mathrm{t}}=\frac{1}{2}[{\pi }_{11}+{\pi }_{12}-{\pi }_{44}]$

For piezoresistors in the <100> plane of an n-silicon substrate, the maximum piezo coefficient is found along the (100) crystal axis, and the piezo coefficients are reduced to:

(1.11)${\pi }_{\mathrm{l}}={\pi }_{11}$

and

(1.12)${\pi }_{\mathrm{t}}={\pi }_{12}$

It is immediately observed that for both n- and p-type piezoresistors, uniaxially stressed at respective optimum locations for sensitivity, the longitudinal and transverse piezo coefficients have opposite signs. The advantages offered by this fact in a Wheatstone bridge have contributed to the dominance of bridge circuits in piezoresistive sensing based on silicon.

The alignment of piezoresistors to be constructed is governed by the piezoresistive coefficients listed in Table 1.2. Almost universally, the optimal solution is to align the sensing resistors according to maximum piezoresistive effect, as described by the examples depicted in Figure 1.13. The choices of resistor direction, dicing direction, and anisotropic etching are determined by the crystal orientations. In addition, the specification of the crystallographic location of the substrate wafer flat is based on the chosen crystal alignment. The primary flat has historically been located at the <110> direction, and dicing along and perpendicular to the primary flat is depicted in Figure 1.13(a) and (c).

1.1.4.2.6 Effect of Temperature and Doping

In addition to the piezoresistive effect, the silicon resistors exhibit strong temperature dependence. For piezoresistors with low to moderate doping, the resistivity changes can reach one magnitude for every 100°C. Change in offset is caused by leakage currents, which are strongly dependent on temperature according to Laermer [29]. While in some cases the temperature dependence can be utilized or ignored, in the vast majority of cases this must be compensated for. Combined with the effect of doping on the piezoresistive effect, the temperature effect can be corrected with the piezoresistance correction factor P(N,T). Generally, a higher dopant concentration in silicon reduces the temperature effect, whereas the higher the temperature, the lower is the effect of doping level. Thus, designing of the resistor requires a trade-off between sensitivity and temperature stability (Figure 1.14).

Figure 1.14. Piezo correction factor P(N,T) in n-Si as a function of doping level, for various temperatures.

Redrawn and modified from Kanda [30].

The modern IC technology can provide a mathematical solution to the compensation of the piezoresistors, by introducing signal conditioning of the linearity and temperature effect to the sensing setup. This approach provides additional accuracy and flexibility at the cost of some cost and complexity. While the approach is commonly used to improve nonidealities in surface micromachined sensors, the performance of sensing elements manufactured from bulk, single-crystal silicon is usually close to ideal when temperature effects are accounted for.

Basic solutions for correcting for temperature variations include the use of a reference (i.e., a non-strained resistor which is at the same temperature). The difference of signal between the strained and non-strained sensors provides the desired signal due to strain only. The other basic technique is to utilize a temperature independent circuit—in practice, a bridge circuit.

In a Wheatstone bridge circuit application, the four resistors are doped to the silicon and arranged in such a way on the sensing membrane that they react to strain in pairs. In addition to having the advantages in sensitivity, discussed earlier, the bridge circuit can be used to compensate for temperature effects. The standard setup of a Wheatstone bridge in (100) silicon substrate consists of one pair of resistors aligned to give maximum positive change in resistivity (longitudinally stressed if p-type, transversely stressed if n-type), while the other pair yields the maximum negative change (a perpendicular alignment with respect to the first pair of resistors). This bridge circuit provides an output signal which is independent of temperature, assuming that the whole membrane is subjected to equal temperature changes. The circuit output is thus, to a first-degree approximation, directly proportional to the change in resistivity due to the applied stress. The main disadvantage of piezoresistive gauging using bridge circuits lies in the current requirements in the milliampere range, which cause limitations in the use of these circuits in power-sensitive applications.

1.1.4.2.7 Example of a Piezoresistive Sensor Design

Pressure sensing has utilized piezoresistive sensing based on MEMS technology for years and is the first widely adopted application of the technology. This is due to the fact that thin micromachined silicon membranes with a piezoresistor bridge implemented on top of them provide a rather ideal solution to the common problem of sensing pressure over a known, rather limited range of pressures, over long periods of time and countless cycles of pressure changes, for low cost and no maintenance.

A very basic sensing setup is as follows:

Starting point:

Silicon substrate, N-type, (100) orientation, device dicing along <110> direction.

Membrane defined by etching, using an alkali etchant from the backside of the wafer. The long etching is carried out in concentrated KOH or TMAH, requiring a thick protective layer of oxide, or nitride. The traditional bulk micromachining has utilized backside patterning for these cavity-etching processes.

Cavity sealed through wafer bonding. The sealing options range from glues and glass frits to fusion bonding of silicon wafers.

Piezoresistors are boron implanted on top of the wafer, at the edges of the membrane, where the stress maxims are located when the cavity pressure differs from the outside pressure. Boron implantation of the ohmic contacts can usually also be performed at this stage.

The basic device is finished with one or two layers of metals.

The dopant profile of a simple implanted and diffused piezoresistor of the type described is illustrated in Figure 1.15. The denuded zone responsible for the electrical isolation is shown without bias; with reverse bias, it can be extended to meet the requirements.

Figure 1.15. Basic diffused piezoresistor dopant depth profile. The wafer surface is to the left, and the piezoresistor is hatched. The transition zone under the piezoresistor acts as the electrical isolation. The hatched line (– · · –) on the left denotes free hole concentration, and the hatched line (— · —) on the right side of the transition denotes free electron density, approaching the starting material N_D density in the depth of the wafer. The graph is calculated using IC-simulation software ICECREM 4.3 for WINDOWS™ by Fraunhofer Gesellschaft for Integrated Systems and Device Technology (IISB), Erlangen, Germany [31], and the carrier concentrations refer to zero bias.

The basic device outlined earlier follows the geometry outlined in Figure 1.16. This device has the piezoresistors located at the stress maximums of the rectangular membrane and along the crystal axis yielding greatest change in resistivity for a given stress. Also, the shear stresses of the membrane are minimized, theoretically to zero, at the locations of the resistors.

Figure 1.16. Basic MEMS-based sensor application using piezoresistors in &lt;100&gt; silicon. (a) Side view (cross-section along the &lt;110&gt; plane). (b) Top view, with the piezoresistors located in a Wheatstone bridge, along the (110) direction on the top of the silicon membrane.

1.1 General background

In recent years, there has been great deal of efforts by chemists and physicists to discover novel nanomaterials for different applications (Haque et al., 2018). One of the largely moving areas of chemical research is the development of inorganic nanomaterials including metals, semiconductors and insulators in the dimension range of 1–100 nm (Haque et al., 2018). Dynamical behavior of low dimensional semiconductors has also become a crucial part of recent efforts. This has enabled intense investigations related to their novel optical, mechanical and transport phenomena. A variety of low dimensional semiconductors, which include quantum wires, quantum wells and quantum dots are made available (Xu et al., 2018). Of these, quantum dots have gained much popularity (Chen et al., 2019) Quantum dots are the zero-dimensional structures in which electrons are delocalized along all the three spatial dimensions, leading to ‘quantum confinement effect’ (Rao et al., 2019a; Chakraborty et al., 2019). Quantum confinement occurs when the size of the nanocrystal becomes smaller compared with twice the Bohr radius, which then becomes weak, when it exceeds the Bohr radius (Bergren et al., 2016).

In semiconductor nanocrystals, when a photon absorbs energy greater than that of the semiconductor band gap, it results in the generation of electron-hole pairs or excitons in which electrons and holes are bound by electrostatic attraction. The average distance between an electron and the hole into an exciton is of the order of Bohr radius. The optical and electrical properties of semiconductor nanocrystal then becomes dependent upon its physical dimensions when its size approaches near to that of the Bohr radius (Chakraborty et al., 2019).

Luminescent semiconductor quantum dots exhibit remarkable photostability, broad absorption profiles, high quantum yields and photo bleaching stability. Controlled shape and size luminescent characteristics of quantum dots arise from the quantum confinement effect, which allow accomplishment of related materials like optical visual for equivalent investigation of dissimilar analytes. The large stokes and slender emission bands shift in the luminescence spectra of quantum dots enable efficient coupling of other fluorophores or quantum dots with the emitted light (Owen and Brus, 2017). Hence, these systems have been widely explored as the potential materials for multicolored photoluminescent probes, luminescent biological labels, markers in imaging, emitters in light emitting diodes, gain media in lasers, light harvester in photovoltaics, photocatalysis and in various environmental treatment applications (Sundheep et al., 2019; Ramachandran et al., 2019; Mallick et al., 2019).

1.2 Need for sustainable development

Clean environment, water and energy are the basic needs for human survival and economic development (Gopinath et al., 2019). However, the rise in demand for various products has led the manufacturers to indulge in risky, but profitable production modes, leading to long-term environmental threats (Zandi et al., 2019). Additionally, utilization of energy through fossil fuels such as petroleum, natural gas and coal has led to pollution of air and water bodies (BusaidiBaawain et al., 2019). The limited availability of fossil fuels and their increasing year-wise unregulated consumption may lead to energy crises of the future. Since the Kyoto protocol in 2005, these issues have emerged in the global scenario in a highly debatable manner (Chen and Chen, 2002). Formulation and implementation of an integrated set of policies addressing the energy and environmental concerns simultaneously have met with several challenges in a developed nation such as the United States of America (Greening and Bernow, 2004). However, the present policies and technologies are ineffective in the realization of long-term goals (Andrews and Govil, 1995). In order to tackle fossil fuel-based energy crisis and environmental pollution, there is a greater need for greener and sustainable source, which can resolve both the energy and the environment related issues.

Nanotechnology can be a highly promising field for development of sustainability. It is an emerging field, which could contribute for the development of smarter materials capable of both generating energy and degrading the environmental toxic pollutants. It deals with designing and manipulation of materials at the molecular scale. Rapid development of novel nanomaterials can create options regarding new product innovation and high performance applications (Jyothi et al., 2019). Fabrication of such novel functional materials with tunable sizes, shapes, crystallinity, porosity and structures are of great importance for novel innovations in sustainable energy technologies (RoyDas et al., 2019). It also allows the fabrication of materials having specific functionalities capable of recognizing a particular pollutant in a mixture (Dharupaneedi et al., 2019). Thus, tremendous progress in nanotechnology may lead to the basic understanding of physics at the nanoscale in order to control the system properties and searching for new materials for energy and environmental applications (Chung et al., 2012).

Low energy solution-based synthesis of nanomaterials would allow their incorporation into the devices (Bera et al., 2019). Among the nanomaterials, photoactive metal oxide nanoparticles, quantum dots and carbon-based nanomaterials are the potential candidature since they rely upon the sunlight, which itself is a clean and sustainable energy source. Quantum confinement effect in nanomaterials such as quantum dots has given rise to many of the fascinating optoelectronic features, which make them highly eligible candidates for energy and environment-based applications. Moreover, such smart functional materials may be helpful in the development of clean and sustainable energy sources as well as for water and air purification-based devices. Carbon-based nanocomposites such as carbon quantum dots (CQDs) may play a significant role in this regard due to their distinctive optoelectronic properties. In recent years, these carbon-based eco-friendly materials have been widely investigated for photovoltaic applications, water splitting and their ability to degrade harmful pollutants (Sarkar et al., 2016; Reddy et al., 2019a, 2019b; Mishra et al., 2019a; Rao et al., 2019b).

1.3 Carbon quantum dots (CQDs)

Carbon-based nanomaterials have gained much significance owing to their outstanding optical, electronic, mechanical and optical characteristics (Sarkar et al., 2016). Among them, carbon dots (CDs) have the greatest consideration due to their biocompatibility, abundance of raw materials in the nature, low toxicity, resistance to photo-bleaching and cost-effectiveness (Wang et al., 2014). With their sizes in the range of 1–10 nm, these materials are classified as polymer dots (PDs), graphene quantum dots (GQDs), and carbon quantum dots (CQDs) (Sarkar et al., 2016). CQDs are the zero-dimensional fluorescent carbon nanomaterials possessing sp² hybridized carbon atoms with surfaced passivity for oxygen containing functional groups such as hydroxyl and carboxylic groups. In contrast to other semiconductor CQDs are chemically inert, biocompatible, can be easily functionalized and are resistant to photo-bleaching (Linehan and Doyle, 2014). Their outstanding photo-physical properties, biocompatibility and low-cost make them ideal in the fields of bioimaging (Roy et al., 2019), sensing (Shetti et al., 2019a) and photocatalysis.

Researchers have reported several major developments in CQDs modifications and their applications. However, the issues based on optical and electronic properties are mainly due to the defects in CQDs, agglomeration of CQDs during the synthesis of CQDs affects the uniformity in size and the surface properties. Hitherto, approaches to precisely controlling the defects in CQDs are unavailable. Hence, it is required to put more efforts in atom-precise structural synthesis of CQDs. Also, modification of CQDs with controllable functionalization and doping of CQDs are the crucial issues. The majority of CQDs in photo-catalysis have shown restricted light-harvesting capacity, but only a few reports are available on photo-stability of CQD-based nanocomposites, thus signifying to develop further stable CQD-based photocatalytic systems for useful applications (Duarah and Karak, 2019; Ghosh et al., 2019; Mishra et al., 2019b). In biomedical field, many studies have been reported based on CQDs toxicity and their related mechanism. The C-dots are considered to be the competent nano-architectures for drug delivery and bioimaging, but their poor size and surface characteristics hinder their wider usage (Kaushik et al., 2019; Gulla et al., 2019). In order to overcome the biodegradability and toxicity problems, new fluorescent materials such as CQDs have been developed possessing better optical, biological, chemical inertness, and low toxicity compared to semiconductor quantum dots (Deng et al., 2019).

This timely review summarizes surface modifications and band gap tuning of CQDs by different novel metals and metal oxides. The review will address an outlook on the change in optical properties by surface modifications of CQDs. In later parts, more focus will be placed on water treatment/splitting applications such as heavy metal ion detection, photodegradation of dyes and H₂ production of CQDs. Lastly, limitations and challenges of CQDs will be discussed along with the latest published reports for a quantitative discussion.

1.1 RBS References

An excellent introduction to RBS is found in the surface and thin film analysis textbook by Feldman and Mayer.^[1] Because virtually all III-V device substrates are prepared from single crystal material, the use of channeling in RBS requires much attention. This review draws heavily from the text by Feldman, Mayer, and Picraux^[2] on this subject. Proceedings from the International Ion Beam Analysis meeting are found in Nuclear Instruments and Methods, Part B.

1.2 SIMS References

This review on SIMS characterization of III-V materials is fortunate to have a number of excellent references upon which to draw. An in depth treatise that covers the fundamentals of almost all aspects of SIMS has been written by Benninghoven, Rüdenauer and Werner.^[3] A more recent work, geared mainly to the practice of semiconductor analysis, is by Wilson, Stevie, and Magee.^[4] A similar review to this one, with an emphasis on InP materials has been written by Geva.^[5] The textbook by Feldman and Mayer also has an excellent section on the fundamentals and application of SIMS as well as RBS. Any similarities of this work to these excellent references is purely intentional.

The proceedings of the biannual international conferences on SIMS are excellent sources for keeping up with SIMS technology and applications.^[6] Proceedings of special topics conferences, such as the Molecular Beam Epitaxy Workshop, American Vacuum Society annual meetings, and others, are often published in the Journal of Vacuum Science and Technology. The journal Surface and Interface Analysis also contains articles pertinent to compound semiconductor characterization by SIMS.

The sections of this chapter that deal with sputter-based depth profiling may seem to have an exceptionally large amount of information about sputtered neutral mass spectrometry, or post-ionization techniques, because the author has experience in this field of research. In addition, many of the applications of the techniques covered here will be examples from his institution. This is only for the convenience of obtaining useful illustrations and is not meant to suggest that other institutions are not active in these fields of work.

1.3 Fundamentals of Ion-Solid Interactions

When a high velocity ion strikes the a solid, the ion will transfer some, or all, of its energy to the solid. For singly charged ions, the energy is numerically the same as the acceleration voltage, (E = qV). The manner of energy transfer depends upon many parameters, including the masses of the incident ion and collisional target nuclei and the energy and angle of incidence of the incoming projectile. Low energy ions, (< 100 eV) typically stop on or near the surface, thus building thin films. Incident, or primary ions with 1–20 keV of energy transfer energy to the sample's nuclei, which leads to sputtering, the sequential removal of surface layers, which forms the basis of analysis of the solids by secondary ion mass spectrometry (SIMS). At higher energies, (100–300 keV), ions implant into the solid, modifying its elemental composition. Some sputtering occurs, but most of the ions and their energy are implanted deeply (> 1000 Å) into the solid. Implantation damage and mixing of material hinders the analysis of layered samples with these high energy primary ions. However, ion implantation is widely used to control the electrical properties of semiconductors. MeV ions, especially He ions, penetrate very deeply into the solid (microns), loosing small amounts of energy to the solid's electrons until a scattering event occurs with a nucleus. Minimal damage to the sample occurs because most of the energy remains in the backscattered ion. Accordingly, He ion backscattering affords nondestructive surface and bulk chemical analysis.

10.7.1 Characteristics of Wide Band Gap Semiconductors

Power semiconductor devices made from materials with band gap energies larger than that in Si have been touted for many decades. The potential advantages of these WBG devices include higher achievable junction temperatures and thinner drift regions (because of the associated higher critical electric field values) that can result in much lower on resistance than is possible in Si. WBG semiconductor materials allow power electronic components to be smaller, faster, more reliable, and more efficient than their silicon (Si)-based counterparts. These capabilities make it possible to reduce weight, volume, efficiency, and life-cycle costs in a wide range of power applications. Harnessing these capabilities can lead to dramatic energy savings in industrial processing and consumer appliances, accelerate widespread use of electric vehicles and fuel cells, and help integrate renewable energy onto the electric grid.

At present, SiC is considered to have the best trade-off between properties and commercial maturity with considerable potential for both high temperature applications and high power devices. However, the industrial interest for GaN power devices is increasing recently. For this reason, SiC and GaN are the more attractive candidates to replace Si in such applications. In fact, some SiC devices, such as Schottky diodes, are already competing in the semiconductor market with Si power diodes. Currently, it is a sort of competition between SiC and GaN in a battle of performance versus cost. Nevertheless, scientific and industrial actors agree in considering that both will find the respective application fields with a tremendous potential market. However, many of the material advantages still remain not fully exploited due to specific material quality, technology limitations, nonoptimized device designs, and reliability issues. It is worth mentioning that diamond exhibits the best properties of all the WBG semiconductors. Theoretically diamond would be ideal for bipolar device designs, particularly in operating environments of elevated temperatures. The high values of carrier mobilities, as well as the large band gap and high thermal conductivity, make diamond the ideal future material for electronic devices of all power levels and types. However, there are critical problems related with the crystal growth (small areas single crystal wafers), both p-type and n-type dopings and processing. Therefore, there is not a diamond power device in the market and it is not expected in the next decade. SiC power devices recently reported in literature include high-voltage and high-temperature diodes, junction controlled devices (like junction field effect transistors (JFETs)), MOSFETs and metal-semiconductor-field effect transistors (MESFETs). Those based on GaN include diodes, HEMTs, and MOSFETs; and advanced research on novel devices concerning low-losses digital switches based on SiC and GaN is also of main concern. These novel devices represent a real breakthrough in power devices.

10.7.2 Silicon Carbide Overview

Silicon carbide (SiC) was accidentally discovered in 1890 by Edward G. Acheson, an assistant to Thomas Edison, when he was running an experiment on the synthesis of diamonds. Acheson thought the new material was a compound of carbon and alumina present in the clay, leading him to name it carborundum, a name that is still being used on some occasions. Silicon carbide occurs naturally in meteorites, though very rarely and in very small amounts. Being the discoverer of SiC, Acheson was the first to synthesize SiC by passing an electric current through a mixture of clay and carbon. Today, SiC is still produced via a solid-state reaction between sand (silicon dioxide) and petroleum coke (carbon) at very high temperatures in an electric arc furnace.

Silicon carbide is a semiconductor material with highly suitable properties for high-power, high-frequency, and high-temperature applications. This almost worn-out opening statement may be found in many papers dealing with SiC. Yet, it cannot be left out because it really brings forward the essence of the material's potential. Silicon carbide is a WBG semiconductor material with high breakdown electric field strength, high saturated drift velocity of electrons, and a high thermal conductivity. Therefore, these properties make SiC ideally suited for a vast number of applications. Today there are high-frequency metal-semiconductor-field effect transistors offered commercially, as well as an emerging market for Schottky diodes made from SiC.

10.7.3 Silicon Carbide Devices

In this section, an overview of the available SiC devices is given. The dramatic quality improvement of the SiC material in combination with excellent research and development efforts on the design and fabrication of SiC devices by several research groups has recently resulted in a strong commercialization of SiC switch-mode devices. Nevertheless, the SiC device market is still in an early stage, and today, some available SiC switches are the JFET, BJT, MOSFET, and Schottky barrier diodes (SBDs). Commercially available SiC devices are still not in mass production. Finally, it is also worth mentioning the progress of the research on the SiC IGBT.

10.7.3.2 SiC MOSFET

Several years have been spent on the research and development of the SiC MOSFET. The fabrication and stability of this oxide layer has been challenging. SiC oxides are not showing the same reliability as in Si MOSFETs. They have higher threshold voltage shifts, gate leakage, and oxide failures than comparably biased silicon MOSFET's. This has detrimental impact on SiO₂ electrical quality. Consequently, much longer and higher temperature maintenance (annealing) is required to improve the SiC oxide quality. A cross section of a popular commercialized vertical double implanted SiC MOSFET structure is shown in Fig. 10.52. The normally-off behavior of the SiC MOSFET makes it attractive to the designers of power electronic converters. Unfortunately, the low channel mobility cause additional conduction-state resistance of the device, and thus increases conduction-state power losses. Additionally, the reliability and the stability of the gate oxide layer, especially over long time periods and at elevated temperatures, have not been confirmed yet. Fabrication issues also contribute to the deceleration of SiC MOSFET development.

Figure 10.52. Cross section of 4H-SiC vertical double implanted MOSFET.

10.7.3.4 SiC Bipolar Junction Transistor

The SiC BJT is a bipolar normally-off device, which combines both a low conduction-state voltage drop (0.32 V at 100 A/cm²) and a quite fast switching performance. A cross section of this device is shown in Fig. 10.53 where it is obvious that this is an npn BJT. The low conduction-state voltage drop is obtained because of the cancellation of the base–emitter and base–collector junction voltages. The SiC BJT is a current-driven device, which means that a substantial continuous current is required as long as it conducts a collector current.

Figure 10.53. Cross section of SiC BJT.

10.7.3.5 SiC Junction Field Effect Transistor

A JFET has no SiO₂–SiC interface and could, therefore, be available as a commercial power device in the next few years. The high quality of the conduction channel and good control of the channel dimensions and doping are crucial for the JFET performance. The normally-on JFET design is capable of extremely low conduction-state resistance. Normally-on JFETs are not easily accepted by the market due to system safety requirements, regardless of their excellent on resistance. Normally-off JFETs on the other hand require a narrow and relatively low-doped channel to ensure the N-off performance, and thus pay a penalty in terms of the conduction-state performance. Normally-off JFETs are also vulnerable to the electromagnetic interference (EMI) noise due to the small range of the gate control voltage. Hence, the gate control circuitry for JFETs requires special attention to ensure reliable operation. In the case of normally-on JFETs the development of inherently safe gate drivers is particularly desired to guarantee the safety of the whole system. A significant difference between the JFET and the MOSFET is that the MOSFET is normally-off, whereas the JFET can be either normally-on or normally-off. Normally-on means that the JFET conducts when no voltage is applied to the gate. Fig. 10.54 shows the JFETs symbols and the equivalent circuit of the n-type.

Figure 10.54. SiC junction field effect transistor symbols and equivalent circuit.

(a) Symbols; (b) equivalent circuit of the n-type.

Fig. 10.55 presents the i_D–v_GS characteristic in the saturation region of a SiC JFET. As can be seen from Fig. 10.55, the slope of the characteristic is equal to β^0.5, and the value of the threshold voltage is defined as that voltage of v_GS for which the drain current I_D is approximately zero. Moreover, Fig. 10.56 presents the i_D–v_DS characteristic of a SiC JFET (Table 10.3).

Figure 10.55. Normally-on SiC junction field effect transistor i_D–v_GS input characteristic for a certain value of V_DS.

Figure 10.56. Normally-on SiC junction field effect transistor i_D–v_DS output characteristic.

Table 10.3. SiC junction field effect transistor model parameters

Name	Parameter	Units
VTO	Threshold voltage, Vth	V
Beta	Transconductance, β	A/V2
Lamda	Channel length modulation parameter, λ	V−1
Rd	Drain ohmic resistance	Ohm
Rs	Source ohmic resistance	Ohm
Is	Gate junction saturation current	A
Cgs	Zero-bias G–S junction capacitance	F
Cgd	Zero-bias G–D junction capacitance	F
PB	Gate junction potential	V
M	Junction grading coefficient	–
KF	Flicker-noise coefficient	–
AF	Flicker-noise exponent	–
FC	Coefficient for forward-bias depletion capacitance formula	–
TNOM	Parameter measurement temperature	°C
XTI	IS temperature coefficient	–
VTOTC	Threshold voltage temperature coefficient	V/°C
BETATC	Transconductance exponential temperature coefficient	°C−1

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Lateral channel junction field effect transistor (LCJFET)

The most successful JFET type in terms of voltage and current ratings has been the lateral channel JFET. The cross section of the LCJFET is shown in Fig. 10.57. The LCJFET allows optimal control of the channel parameters and offers the largest ease of fabrication compared to other concepts. It also offers the use of the inherent body diode as an antiparallel diode in switching applications since the buried gate is preferably connected to source. This is necessary to reduce the Miller capacitance, and thus maintain high speed operation. The original LCJFET structure uses ion-implantation for the gate and the base region, and planar epitaxial growth for the defect-free channel layer. This leads to advantages in terms of ease of fabrication, freedom of parameter choice due to a wide design window, and small fabrication tolerances. Its main disadvantage is a relative large specific on resistance, which is related to the large cell pitch due to the lateral configuration of the channel.

Figure 10.57. Cross section of SiC lateral channel junction field effect transistor.

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Vertical trench junction field effect transistor (VTJFET)

The cross section of a VTJFET is shown in Fig. 10.58. The VTJFET SiC JFET can be either a normally-off (enhancement-mode VTJFET—EMVTJFET) or a normally-on (depletion-mode VTJFET—DMVTJFET) device, depending on the thickness of the vertical channel and the doping levels of the structure. As other normally-on JFET designs, a negative gate-source voltage is necessary to keep it in the cut-off mode. On the other hand, a significant gate current (approximately 200 mA for a 30-A device) is necessary for the normally-off JFET to keep it in the conduction mode. The pinch-off voltage for the DMVJFET equals approximately −6 V, whereas the positive pinch-off voltage for the normally-off one is slightly higher than 1 V. Comparing this type of SiC JFETs to the LCJFET there is no physical antiparallel body diode in this design. However, the VTJFET can conduct current in the reverse direction. When the vertical channel JFETs are used for freewheeling purpose, the reverse-recovery currents are only caused by the depletion charge of the device and no minority injection is involved.

Figure 10.58. Cross-section of vertical trench junction field effect transistor.

Fig. 10.59 presents the heat sinks of two inverter stages of the same power one implemented with Si IGBTs and the other with SiC JFETs. As can be seen from Fig. 10.59, the power semiconductor stage of the SiC inverter is exhibiting higher power density (W/cm²) due to the higher efficiency.

Figure 10.59. Heat sinks of two inverter stages of the same power but with different semiconductor devices.

(a) Using Si semiconductor devices; (b) using SiC semiconductor devices.

Fig. 10.60 shows the power circuit of a three-phase voltage source inverter implemented with SiC JFETs.

Figure 10.60. Three-phase inverter implemented using normally-on SiC junction field effect transistors.

Fig. 10.61 shows a driving circuit of a normally-on SiC JFET. Since the normally-on SiC JFET needs 0 V at its gate to turn on and −15 V to turn off the conventional pulses of +15 are converted through the totem pole MOSFETs (IXDD_609) to −15 V pulses.

Figure 10.61. Driving circuit for normally-on SiC junction field effect transistors.

Fig. 10.62 shows a driving circuit of a normally-off SiC JFET.

Figure 10.62. Driving circuit for normally-off SiC junction field effect transistors.

When an inverter is implemented with SiC JFETs, it is important to solve the Miller effect; otherwise unwanted overvoltage effects may appear across the semiconductor devices. Fig. 10.63 shows the Miller effect on one phase leg of an inverter. Specifically, when the upper SiC JFET is in the turn-on transition and the lower is in the cut-off mode, then the voltage of the lower JFET drain increases very fast from 0 to +V_in with a very high dv/dt. Since the semiconductor switch S₂ is conducting the parasitic current I_CGD, which is generated from Miller capacitance C_GD, will flow through the resistor R_gl toward the ground increasing the voltage V_GS. If V_GS = − V_gg + R_gl·I_GCD is increased above its threshold voltage value, then S₂ might go faulty to conduction and together with S₁ a short-circuit is created on the phase leg which will be catastrophic for both semiconductor switches.

Figure 10.63. SiC junction field effect transistor Miller effect on an inverter leg.