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[ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-A
Summary: Add support for vcadd_* family of intrinsics. This set of intrinsics is available in Armv8.3-A. The fp16 versions require the FP16 extension, which has been available (opt-in) since Armv8.2-A. Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70862
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‎clang/include/clang/Basic/arm_neon.td

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@@ -1673,3 +1673,21 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in {
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def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi>;
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def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi>;
16751675
}
1676+
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// v8.3-A Vector complex addition intrinsics
1678+
let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1679+
def VCADD_ROT90_FP16 : SInst<"vcadd_rot90", "...", "h">;
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def VCADD_ROT270_FP16 : SInst<"vcadd_rot270", "...", "h">;
1681+
def VCADDQ_ROT90_FP16 : SInst<"vcaddq_rot90", "QQQ", "h">;
1682+
def VCADDQ_ROT270_FP16 : SInst<"vcaddq_rot270", "QQQ", "h">;
1683+
}
1684+
let ArchGuard = "defined(__ARM_FEATURE_COMPLEX)" in {
1685+
def VCADD_ROT90 : SInst<"vcadd_rot90", "...", "f">;
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def VCADD_ROT270 : SInst<"vcadd_rot270", "...", "f">;
1687+
def VCADDQ_ROT90 : SInst<"vcaddq_rot90", "QQQ", "f">;
1688+
def VCADDQ_ROT270 : SInst<"vcaddq_rot270", "QQQ", "f">;
1689+
}
1690+
let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__aarch64__)" in {
1691+
def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
1692+
def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
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}

‎clang/lib/Basic/Targets/AArch64.cpp

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Original file line numberDiff line numberDiff line change
@@ -158,6 +158,7 @@ void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
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void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
160160
MacroBuilder &Builder) const {
161+
Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
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Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
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// Also include the Armv8.2 defines
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getTargetDefinesARMV82A(Opts, Builder);

‎clang/lib/Basic/Targets/ARM.cpp

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Original file line numberDiff line numberDiff line change
@@ -580,6 +580,13 @@ void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
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getTargetDefinesARMV81A(Opts, Builder);
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}
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583+
void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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// Also include the ARMv8.2-A defines
586+
Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
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getTargetDefinesARMV82A(Opts, Builder);
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}
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583590
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
584591
MacroBuilder &Builder) const {
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// Target identification.
@@ -809,6 +816,11 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
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case llvm::ARM::ArchKind::ARMV8_2A:
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getTargetDefinesARMV82A(Opts, Builder);
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break;
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case llvm::ARM::ArchKind::ARMV8_3A:
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case llvm::ARM::ArchKind::ARMV8_4A:
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case llvm::ARM::ArchKind::ARMV8_5A:
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getTargetDefinesARMV83A(Opts, Builder);
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break;
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}
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}
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‎clang/lib/Basic/Targets/ARM.h

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@@ -148,9 +148,10 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
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void getTargetDefinesARMV81A(const LangOptions &Opts,
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MacroBuilder &Builder) const;
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void getTargetDefinesARMV82A(const LangOptions &Opts,
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MacroBuilder &Builder) const;
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void getTargetDefinesARMV83A(const LangOptions &Opts,
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MacroBuilder &Builder) const;
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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‎clang/lib/CodeGen/CGBuiltin.cpp

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@@ -4454,6 +4454,10 @@ static const NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
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NEONMAP1(vaesmcq_v, arm_neon_aesmc, 0),
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NEONMAP1(vbsl_v, arm_neon_vbsl, AddRetType),
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NEONMAP1(vbslq_v, arm_neon_vbsl, AddRetType),
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NEONMAP1(vcadd_rot270_v, arm_neon_vcadd_rot270, Add1ArgType),
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NEONMAP1(vcadd_rot90_v, arm_neon_vcadd_rot90, Add1ArgType),
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NEONMAP1(vcaddq_rot270_v, arm_neon_vcadd_rot270, Add1ArgType),
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NEONMAP1(vcaddq_rot90_v, arm_neon_vcadd_rot90, Add1ArgType),
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NEONMAP1(vcage_v, arm_neon_vacge, 0),
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NEONMAP1(vcageq_v, arm_neon_vacge, 0),
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NEONMAP1(vcagt_v, arm_neon_vacgt, 0),
@@ -4727,6 +4731,10 @@ static const NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
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NEONMAP1(vaeseq_v, aarch64_crypto_aese, 0),
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NEONMAP1(vaesimcq_v, aarch64_crypto_aesimc, 0),
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NEONMAP1(vaesmcq_v, aarch64_crypto_aesmc, 0),
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NEONMAP1(vcadd_rot270_v, aarch64_neon_vcadd_rot270, Add1ArgType),
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NEONMAP1(vcadd_rot90_v, aarch64_neon_vcadd_rot90, Add1ArgType),
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NEONMAP1(vcaddq_rot270_v, aarch64_neon_vcadd_rot270, Add1ArgType),
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NEONMAP1(vcaddq_rot90_v, aarch64_neon_vcadd_rot90, Add1ArgType),
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NEONMAP1(vcage_v, aarch64_neon_facge, 0),
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NEONMAP1(vcageq_v, aarch64_neon_facge, 0),
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NEONMAP1(vcagt_v, aarch64_neon_facgt, 0),

‎clang/test/CodeGen/aarch64-neon-vcadd.c

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@@ -0,0 +1,63 @@
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// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a+fp16 %s -S -emit-llvm -o - | FileCheck %s
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#include <arm_neon.h>
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void foo16x4_rot90(float16x4_t a, float16x4_t b)
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{
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// CHECK: call <4 x half> @llvm.aarch64.neon.vcadd.rot90.v4f16
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float16x4_t result = vcadd_rot90_f16(a, b);
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}
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void foo32x2_rot90(float32x2_t a, float32x2_t b)
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{
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// CHECK: call <2 x float> @llvm.aarch64.neon.vcadd.rot90.v2f32
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float32x2_t result = vcadd_rot90_f32(a, b);
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}
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void foo16x8_rot90(float16x8_t a, float16x8_t b)
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{
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// CHECK: call <8 x half> @llvm.aarch64.neon.vcadd.rot90.v8f16
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float16x8_t result = vcaddq_rot90_f16(a, b);
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}
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void foo32x4_rot90(float32x4_t a, float32x4_t b)
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{
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// CHECK: call <4 x float> @llvm.aarch64.neon.vcadd.rot90.v4f32
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float32x4_t result = vcaddq_rot90_f32(a, b);
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}
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void foo64x2_rot90(float64x2_t a, float64x2_t b)
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{
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// CHECK: call <2 x double> @llvm.aarch64.neon.vcadd.rot90.v2f64
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float64x2_t result = vcaddq_rot90_f64(a, b);
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}
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void foo16x4_rot270(float16x4_t a, float16x4_t b)
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{
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// CHECK: call <4 x half> @llvm.aarch64.neon.vcadd.rot270.v4f16
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float16x4_t result = vcadd_rot270_f16(a, b);
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}
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void foo32x2_rot270(float32x2_t a, float32x2_t b)
42+
{
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// CHECK: call <2 x float> @llvm.aarch64.neon.vcadd.rot270.v2f32
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float32x2_t result = vcadd_rot270_f32(a, b);
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}
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void foo16x8_rot270(float16x8_t a, float16x8_t b)
48+
{
49+
// CHECK: call <8 x half> @llvm.aarch64.neon.vcadd.rot270.v8f16
50+
float16x8_t result = vcaddq_rot270_f16(a, b);
51+
}
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void foo32x4_rot270(float32x4_t a, float32x4_t b)
54+
{
55+
// CHECK: call <4 x float> @llvm.aarch64.neon.vcadd.rot270.v4f32
56+
float32x4_t result = vcaddq_rot270_f32(a, b);
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}
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void foo64x2_rot270(float64x2_t a, float64x2_t b)
60+
{
61+
// CHECK: call <2 x double> @llvm.aarch64.neon.vcadd.rot270.v2f64
62+
float64x2_t result = vcaddq_rot270_f64(a, b);
63+
}

‎clang/test/CodeGen/arm-neon-vcadd.c

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@@ -0,0 +1,51 @@
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// RUN: %clang -target arm-arm-none-eabi -march=armv8.3-a+fp16 %s -S -emit-llvm -o - | opt -S -sroa | FileCheck %s
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#include <arm_neon.h>
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void foo16x4_rot90(float16x4_t a, float16x4_t b)
6+
{
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// CHECK: call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16
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float16x4_t result = vcadd_rot90_f16(a, b);
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}
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void foo32x2_rot90(float32x2_t a, float32x2_t b)
12+
{
13+
// CHECK: call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32
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float32x2_t result = vcadd_rot90_f32(a, b);
15+
}
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void foo16x8_rot90(float16x8_t a, float16x8_t b)
18+
{
19+
// CHECK: call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16
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float16x8_t result = vcaddq_rot90_f16(a, b);
21+
}
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23+
void foo32x4_rot90(float32x4_t a, float32x4_t b)
24+
{
25+
// CHECK: call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32
26+
float32x4_t result = vcaddq_rot90_f32(a, b);
27+
}
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29+
void foo16x4_rot270(float16x4_t a, float16x4_t b)
30+
{
31+
// CHECK: call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16
32+
float16x4_t result = vcadd_rot270_f16(a, b);
33+
}
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35+
void foo32x2_rot270(float32x2_t a, float32x2_t b)
36+
{
37+
// CHECK: call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32
38+
float32x2_t result = vcadd_rot270_f32(a, b);
39+
}
40+
41+
void foo16x8_rot270(float16x8_t a, float16x8_t b)
42+
{
43+
// CHECK: call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16
44+
float16x8_t result = vcaddq_rot270_f16(a, b);
45+
}
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47+
void foo32x4_rot270(float32x4_t a, float32x4_t b)
48+
{
49+
// CHECK: call <4 x float> @llvm.arm.neon.vcadd.rot270.v4f32
50+
float32x4_t result = vcaddq_rot270_f32(a, b);
51+
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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@@ -446,6 +446,10 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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def int_aarch64_neon_fmlsl : AdvSIMD_FP16FML_Intrinsic;
447447
def int_aarch64_neon_fmlal2 : AdvSIMD_FP16FML_Intrinsic;
448448
def int_aarch64_neon_fmlsl2 : AdvSIMD_FP16FML_Intrinsic;
449+
450+
// v8.3-A Floating-point complex add
451+
def int_aarch64_neon_vcadd_rot90 : AdvSIMD_2VectorArg_Intrinsic;
452+
def int_aarch64_neon_vcadd_rot270 : AdvSIMD_2VectorArg_Intrinsic;
449453
}
450454

451455
let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".

‎llvm/include/llvm/IR/IntrinsicsARM.td

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@@ -778,6 +778,10 @@ def int_arm_vctp16 : Intrinsic<[llvm_v8i1_ty], [llvm_i32_ty], [IntrNoMem]>;
778778
def int_arm_vctp32 : Intrinsic<[llvm_v4i1_ty], [llvm_i32_ty], [IntrNoMem]>;
779779
def int_arm_vctp64 : Intrinsic<[llvm_v2i1_ty], [llvm_i32_ty], [IntrNoMem]>;
780780

781+
// v8.3-A Floating-point complex add
782+
def int_arm_neon_vcadd_rot90 : Neon_2Arg_Intrinsic;
783+
def int_arm_neon_vcadd_rot270 : Neon_2Arg_Intrinsic;
784+
781785
// GNU eabi mcount
782786
def int_arm_gnu_eabi_mcount : Intrinsic<[],
783787
[],

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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@@ -757,6 +757,29 @@ defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd,
757757
defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla",
758758
null_frag>;
759759

760+
let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
761+
def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
762+
(FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>;
763+
def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
764+
(FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>;
765+
def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
766+
(FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;
767+
def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
768+
(FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>;
769+
}
770+
let Predicates = [HasComplxNum, HasNEON] in {
771+
def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
772+
(FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>;
773+
def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot270 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
774+
(FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 1))>;
775+
foreach Ty = [v4f32, v2f64] in {
776+
def : Pat<(Ty (int_aarch64_neon_vcadd_rot90 (Ty V128:$Rn), (Ty V128:$Rm))),
777+
(!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 0))>;
778+
def : Pat<(Ty (int_aarch64_neon_vcadd_rot270 (Ty V128:$Rn), (Ty V128:$Rm))),
779+
(!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 1))>;
780+
}
781+
}
782+
760783
// v8.3a Pointer Authentication
761784
// These instructions inhabit part of the hint space and so can be used for
762785
// armv8 targets

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