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[AArch64][SVE] Add ptest intrinsics
Summary: Implements the following intrinsics: * @llvm.aarch64.sve.ptest.any * @llvm.aarch64.sve.ptest.first * @llvm.aarch64.sve.ptest.last Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72398
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7 files changed

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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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@@ -1014,6 +1014,12 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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llvm_i32_ty],
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[IntrNoMem]>;
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1017+
class AdvSIMD_SVE_PTEST_Intrinsic
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: Intrinsic<[llvm_i1_ty],
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[llvm_anyvector_ty,
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LLVMMatchType<0>],
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[IntrNoMem]>;
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class AdvSIMD_SVE_TBL_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
@@ -1552,6 +1558,14 @@ def int_aarch64_sve_pnext : AdvSIMD_Pred1VectorArg_Intrinsic;
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def int_aarch64_sve_punpkhi : AdvSIMD_SVE_PUNPKHI_Intrinsic;
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def int_aarch64_sve_punpklo : AdvSIMD_SVE_PUNPKHI_Intrinsic;
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//
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// Testing predicates
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//
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def int_aarch64_sve_ptest_any : AdvSIMD_SVE_PTEST_Intrinsic;
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def int_aarch64_sve_ptest_first : AdvSIMD_SVE_PTEST_Intrinsic;
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def int_aarch64_sve_ptest_last : AdvSIMD_SVE_PTEST_Intrinsic;
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//
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// Gather loads:
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//

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -1357,6 +1357,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AArch64ISD::UUNPKHI: return "AArch64ISD::UUNPKHI";
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case AArch64ISD::UUNPKLO: return "AArch64ISD::UUNPKLO";
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case AArch64ISD::INSR: return "AArch64ISD::INSR";
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case AArch64ISD::PTEST: return "AArch64ISD::PTEST";
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case AArch64ISD::PTRUE: return "AArch64ISD::PTRUE";
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case AArch64ISD::GLD1: return "AArch64ISD::GLD1";
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case AArch64ISD::GLD1_SCALED: return "AArch64ISD::GLD1_SCALED";
@@ -10889,6 +10890,30 @@ static SDValue tryConvertSVEWideCompare(SDNode *N, unsigned ReplacementIID,
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return SDValue();
1089010891
}
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10893+
static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
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AArch64CC::CondCode Cond) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDLoc DL(Op);
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EVT OpVT = Op.getValueType();
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assert(OpVT.isScalableVector() && TLI.isTypeLegal(OpVT) &&
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"Expected legal scalable vector type!");
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// Ensure target specific opcodes are using legal type.
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EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
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SDValue TVal = DAG.getConstant(1, DL, OutVT);
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SDValue FVal = DAG.getConstant(0, DL, OutVT);
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// Set condition code (CC) flags.
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SDValue Test = DAG.getNode(AArch64ISD::PTEST, DL, MVT::Other, Pg, Op);
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// Convert CC to integer based on requested condition.
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// NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
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SDValue CC = DAG.getConstant(getInvertedCondCode(Cond), DL, MVT::i32);
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SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);
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return DAG.getZExtOrTrunc(Res, DL, VT);
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}
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static SDValue performIntrinsicCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const AArch64Subtarget *Subtarget) {
@@ -10989,6 +11014,15 @@ static SDValue performIntrinsicCombine(SDNode *N,
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case Intrinsic::aarch64_sve_cmpls_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmphs, true,
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DCI, DAG);
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case Intrinsic::aarch64_sve_ptest_any:
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return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
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AArch64CC::ANY_ACTIVE);
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case Intrinsic::aarch64_sve_ptest_first:
11021+
return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
11022+
AArch64CC::FIRST_ACTIVE);
11023+
case Intrinsic::aarch64_sve_ptest_last:
11024+
return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
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AArch64CC::LAST_ACTIVE);
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}
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return SDValue();
1099411028
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,7 @@ enum NodeType : unsigned {
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TBL,
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INSR,
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PTEST,
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PTRUE,
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// Unsigned gather loads.

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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Original file line numberDiff line numberDiff line change
@@ -73,6 +73,9 @@ def AArch64clastb_n : SDNode<"AArch64ISD::CLASTB_N", SDT_AArch64ReduceWithIn
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def SDT_AArch64Rev : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
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def AArch64rev : SDNode<"AArch64ISD::REV", SDT_AArch64Rev>;
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def SDT_AArch64PTest : SDTypeProfile<0, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
77+
def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
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7679
let Predicates = [HasSVE] in {
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7881
def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr">;
@@ -1086,6 +1089,15 @@ let Predicates = [HasSVE] in {
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def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
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(FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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1092+
def : Pat<(AArch64ptest (nxv16i1 PPR:$pg), (nxv16i1 PPR:$src)),
1093+
(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(AArch64ptest (nxv8i1 PPR:$pg), (nxv8i1 PPR:$src)),
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(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(AArch64ptest (nxv4i1 PPR:$pg), (nxv4i1 PPR:$src)),
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(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(AArch64ptest (nxv2i1 PPR:$pg), (nxv2i1 PPR:$src)),
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(PTEST_PP PPR:$pg, PPR:$src)>;
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def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
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def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
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def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;

‎llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -250,7 +250,13 @@ enum CondCode { // Meaning (integer) Meaning (floating-point)
250250
AL = 0xe, // Always (unconditional) Always (unconditional)
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NV = 0xf, // Always (unconditional) Always (unconditional)
252252
// Note the NV exists purely to disassemble 0b1111. Execution is "always".
253-
Invalid
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Invalid,
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255+
// Common aliases used for SVE.
256+
ANY_ACTIVE = NE, // (!Z)
257+
FIRST_ACTIVE = MI, // ( N)
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LAST_ACTIVE = LO, // (!C)
259+
NONE_ACTIVE = EQ // ( Z)
254260
};
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256262
inline static const char *getCondCodeName(CondCode Code) {

‎llvm/test/CodeGen/AArch64/sve-intrinsics-pred-testing.ll

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@@ -0,0 +1,36 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; PTEST
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;
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define i1 @ptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: ptest_any:
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; CHECK: ptest p0, p1.b
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; CHECK-NEXT: cset w0, ne
11+
; CHECK-NEXT: ret
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%out = call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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ret i1 %out
14+
}
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define i1 @ptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
17+
; CHECK-LABEL: ptest_first:
18+
; CHECK: ptest p0, p1.b
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; CHECK-NEXT: cset w0, mi
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; CHECK-NEXT: ret
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%out = call i1 @llvm.aarch64.sve.ptest.first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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ret i1 %out
23+
}
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define i1 @ptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
26+
; CHECK-LABEL: ptest_last:
27+
; CHECK: ptest p0, p1.b
28+
; CHECK-NEXT: cset w0, lo
29+
; CHECK-NEXT: ret
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%out = call i1 @llvm.aarch64.sve.ptest.last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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ret i1 %out
32+
}
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declare i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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declare i1 @llvm.aarch64.sve.ptest.first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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declare i1 @llvm.aarch64.sve.ptest.last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)

‎llvm/test/CodeGen/AArch64/sve-setcc.ll

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@@ -0,0 +1,26 @@
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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3+
; Ensure we use the inverted CC result of SVE compare instructions when branching.
4+
define void @sve_cmplt_setcc_inverted(<vscale x 8 x i16>* %out, <vscale x 8 x i16> %in, <vscale x 8 x i1> %pg) {
5+
; CHECK-LABEL: @sve_cmplt_setcc_inverted
6+
; CHECK: cmplt p1.h, p0/z, z0.h, #0
7+
; CHECK-NEXT: ptest p0, p1.b
8+
; CHECK-NEXT: b.ne
9+
entry:
10+
%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %in, <vscale x 2 x i64> zeroinitializer)
11+
%1 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %0)
12+
br i1 %1, label %if.end, label %if.then
13+
14+
if.then:
15+
tail call void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16> %in, <vscale x 8 x i16>* %out, i32 2, <vscale x 8 x i1> %pg)
16+
br label %if.end
17+
18+
if.end:
19+
ret void
20+
}
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22+
declare i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
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26+
declare void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>*, i32, <vscale x 8 x i1>)

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