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davemgreendavemgreen
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[ARM] Reegenerate MVE tests. NFC
The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
1 parent 188f9a3 commit 1b264a8

7 files changed

+309
-123
lines changed

‎llvm/test/CodeGen/Thumb2/mve-phireg.ll

Lines changed: 176 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,101 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
23

34
; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.
45

56
define arm_aapcs_vfpcc void @k() {
67
; CHECK-LABEL: k:
7-
; CHECK: vstrw.32
8-
; CHECK: vldrw.u32
8+
; CHECK: @ %bb.0: @ %entry
9+
; CHECK-NEXT: .save {r4, r5, r6, lr}
10+
; CHECK-NEXT: push {r4, r5, r6, lr}
11+
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
12+
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
13+
; CHECK-NEXT: .pad #16
14+
; CHECK-NEXT: sub sp, #16
15+
; CHECK-NEXT: adr r5, .LCPI0_0
16+
; CHECK-NEXT: adr r4, .LCPI0_1
17+
; CHECK-NEXT: vldrw.u32 q5, [r5]
18+
; CHECK-NEXT: vldrw.u32 q6, [r4]
19+
; CHECK-NEXT: vmov.i32 q0, #0x1
20+
; CHECK-NEXT: vmov.i8 q1, #0x0
21+
; CHECK-NEXT: vmov.i8 q2, #0xff
22+
; CHECK-NEXT: vmov.i16 q3, #0x6
23+
; CHECK-NEXT: vmov.i16 q4, #0x3
24+
; CHECK-NEXT: movs r0, #0
25+
; CHECK-NEXT: .LBB0_1: @ %vector.body
26+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
27+
; CHECK-NEXT: vand q5, q5, q0
28+
; CHECK-NEXT: vand q6, q6, q0
29+
; CHECK-NEXT: vcmp.i32 eq, q5, zr
30+
; CHECK-NEXT: vpsel q5, q2, q1
31+
; CHECK-NEXT: vcmp.i32 eq, q6, zr
32+
; CHECK-NEXT: vpsel q7, q2, q1
33+
; CHECK-NEXT: vmov r1, s28
34+
; CHECK-NEXT: vmov.16 q6[0], r1
35+
; CHECK-NEXT: vmov r1, s29
36+
; CHECK-NEXT: vmov.16 q6[1], r1
37+
; CHECK-NEXT: vmov r1, s30
38+
; CHECK-NEXT: vmov.16 q6[2], r1
39+
; CHECK-NEXT: vmov r1, s31
40+
; CHECK-NEXT: vmov.16 q6[3], r1
41+
; CHECK-NEXT: vmov r1, s20
42+
; CHECK-NEXT: vmov.16 q6[4], r1
43+
; CHECK-NEXT: vmov r1, s21
44+
; CHECK-NEXT: vmov.16 q6[5], r1
45+
; CHECK-NEXT: vmov r1, s22
46+
; CHECK-NEXT: vmov.16 q6[6], r1
47+
; CHECK-NEXT: vmov r1, s23
48+
; CHECK-NEXT: vmov.16 q6[7], r1
49+
; CHECK-NEXT: vcmp.i16 ne, q6, zr
50+
; CHECK-NEXT: vmov.i32 q6, #0x0
51+
; CHECK-NEXT: vpsel q5, q4, q3
52+
; CHECK-NEXT: vstrh.16 q5, [r0]
53+
; CHECK-NEXT: vmov q5, q6
54+
; CHECK-NEXT: cbz r0, .LBB0_2
55+
; CHECK-NEXT: le .LBB0_1
56+
; CHECK-NEXT: .LBB0_2: @ %for.cond4.preheader
57+
; CHECK-NEXT: movs r6, #0
58+
; CHECK-NEXT: cbnz r6, .LBB0_5
59+
; CHECK-NEXT: .LBB0_3: @ %for.body10
60+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
61+
; CHECK-NEXT: cbnz r6, .LBB0_4
62+
; CHECK-NEXT: le .LBB0_3
63+
; CHECK-NEXT: .LBB0_4: @ %for.cond4.loopexit
64+
; CHECK-NEXT: bl l
65+
; CHECK-NEXT: .LBB0_5: @ %vector.body105.preheader
66+
; CHECK-NEXT: vldrw.u32 q0, [r5]
67+
; CHECK-NEXT: vldrw.u32 q1, [r4]
68+
; CHECK-NEXT: vmov.i32 q2, #0x8
69+
; CHECK-NEXT: .LBB0_6: @ %vector.body105
70+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
71+
; CHECK-NEXT: vadd.i32 q1, q1, q2
72+
; CHECK-NEXT: vadd.i32 q0, q0, q2
73+
; CHECK-NEXT: cbz r6, .LBB0_7
74+
; CHECK-NEXT: le .LBB0_6
75+
; CHECK-NEXT: .LBB0_7: @ %vector.body115.ph
76+
; CHECK-NEXT: vldrw.u32 q0, [r4]
77+
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
78+
; CHECK-NEXT: @APP
79+
; CHECK-NEXT: nop
80+
; CHECK-NEXT: @NO_APP
81+
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
82+
; CHECK-NEXT: vmov.i32 q0, #0x4
83+
; CHECK-NEXT: .LBB0_8: @ %vector.body115
84+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
85+
; CHECK-NEXT: vadd.i32 q1, q1, q0
86+
; CHECK-NEXT: b .LBB0_8
87+
; CHECK-NEXT: .p2align 4
88+
; CHECK-NEXT: @ %bb.9:
89+
; CHECK-NEXT: .LCPI0_0:
90+
; CHECK-NEXT: .long 4 @ 0x4
91+
; CHECK-NEXT: .long 5 @ 0x5
92+
; CHECK-NEXT: .long 6 @ 0x6
93+
; CHECK-NEXT: .long 7 @ 0x7
94+
; CHECK-NEXT: .LCPI0_1:
95+
; CHECK-NEXT: .long 0 @ 0x0
96+
; CHECK-NEXT: .long 1 @ 0x1
97+
; CHECK-NEXT: .long 2 @ 0x2
98+
; CHECK-NEXT: .long 3 @ 0x3
999
entry:
10100
br label %vector.body
11101

@@ -56,8 +146,90 @@ vector.body115: ; preds = %vector.body115, %ve
56146

57147
define dso_local i32 @e() #0 {
58148
; CHECK-LABEL: e:
59-
; CHECK: vstrw.32
60-
; CHECK: vldrw.u32
149+
; CHECK: @ %bb.0: @ %entry
150+
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
151+
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
152+
; CHECK-NEXT: .pad #4
153+
; CHECK-NEXT: sub sp, #4
154+
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
155+
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
156+
; CHECK-NEXT: .pad #440
157+
; CHECK-NEXT: sub sp, #440
158+
; CHECK-NEXT: vldr s20, .LCPI1_0
159+
; CHECK-NEXT: movw r9, :lower16:.L_MergedGlobals
160+
; CHECK-NEXT: vldr s23, .LCPI1_1
161+
; CHECK-NEXT: movt r9, :upper16:.L_MergedGlobals
162+
; CHECK-NEXT: mov.w r8, #4
163+
; CHECK-NEXT: mov r5, r9
164+
; CHECK-NEXT: strh.w r8, [sp, #438]
165+
; CHECK-NEXT: movs r6, #0
166+
; CHECK-NEXT: vstr s23, [sp, #48]
167+
; CHECK-NEXT: mov r7, r9
168+
; CHECK-NEXT: vstr s23, [sp, #40]
169+
; CHECK-NEXT: movw r4, :lower16:e
170+
; CHECK-NEXT: ldr r1, [r5, #4]!
171+
; CHECK-NEXT: movt r4, :upper16:e
172+
; CHECK-NEXT: str r6, [sp, #76]
173+
; CHECK-NEXT: vmov s5, r4
174+
; CHECK-NEXT: vmov.32 q7[0], r5
175+
; CHECK-NEXT: ldr r0, [r7, #8]!
176+
; CHECK-NEXT: vmov q0, q7
177+
; CHECK-NEXT: ldr r2, [sp, #48]
178+
; CHECK-NEXT: vmov.32 q0[1], r5
179+
; CHECK-NEXT: vmov s21, r5
180+
; CHECK-NEXT: vmov.32 q0[2], r2
181+
; CHECK-NEXT: ldr r2, [sp, #40]
182+
; CHECK-NEXT: vdup.32 q2, r5
183+
; CHECK-NEXT: vmov.32 q4[0], r7
184+
; CHECK-NEXT: vmov q6, q4
185+
; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
186+
; CHECK-NEXT: vmov.32 q6[1], r2
187+
; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload
188+
; CHECK-NEXT: vmov.f32 s22, s21
189+
; CHECK-NEXT: vmov.32 q6[2], r7
190+
; CHECK-NEXT: vmov.f32 s4, s20
191+
; CHECK-NEXT: vstrw.32 q2, [sp, #16] @ 16-byte Spill
192+
; CHECK-NEXT: vmov.f32 s6, s21
193+
; CHECK-NEXT: vmov.32 q3[0], r4
194+
; CHECK-NEXT: vmov.32 q2[1], r4
195+
; CHECK-NEXT: vmov.32 q6[3], r4
196+
; CHECK-NEXT: vmov.32 q0[3], r4
197+
; CHECK-NEXT: vmov.f32 s7, s23
198+
; CHECK-NEXT: str r1, [sp, #72]
199+
; CHECK-NEXT: vstrw.32 q6, [sp, #124]
200+
; CHECK-NEXT: str r1, [r0]
201+
; CHECK-NEXT: movs r1, #64
202+
; CHECK-NEXT: str r0, [r0]
203+
; CHECK-NEXT: vstrw.32 q5, [sp, #92]
204+
; CHECK-NEXT: vstrw.32 q1, [r0]
205+
; CHECK-NEXT: vstrw.32 q2, [r0]
206+
; CHECK-NEXT: vstrw.32 q3, [r0]
207+
; CHECK-NEXT: vstrw.32 q0, [r0]
208+
; CHECK-NEXT: bl __aeabi_memclr4
209+
; CHECK-NEXT: vstr s23, [sp, #44]
210+
; CHECK-NEXT: vmov.32 q7[1], r7
211+
; CHECK-NEXT: ldr r0, [sp, #44]
212+
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
213+
; CHECK-NEXT: vmov.32 q4[1], r4
214+
; CHECK-NEXT: vmov.32 q7[2], r5
215+
; CHECK-NEXT: vmov.32 q4[2], r5
216+
; CHECK-NEXT: vmov.32 q0[0], r6
217+
; CHECK-NEXT: vmov.32 q4[3], r7
218+
; CHECK-NEXT: vmov.32 q7[3], r0
219+
; CHECK-NEXT: vstrw.32 q4, [r0]
220+
; CHECK-NEXT: str.w r6, [r9]
221+
; CHECK-NEXT: vstrw.32 q0, [r0]
222+
; CHECK-NEXT: vstrw.32 q7, [r0]
223+
; CHECK-NEXT: str.w r8, [sp, #356]
224+
; CHECK-NEXT: .LBB1_1: @ %for.cond
225+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
226+
; CHECK-NEXT: b .LBB1_1
227+
; CHECK-NEXT: .p2align 2
228+
; CHECK-NEXT: @ %bb.2:
229+
; CHECK-NEXT: .LCPI1_0:
230+
; CHECK-NEXT: .long 4 @ float 5.60519386E-45
231+
; CHECK-NEXT: .LCPI1_1:
232+
; CHECK-NEXT: .long 0 @ float 0
61233
entry:
62234
%f = alloca i16, align 2
63235
%g = alloca [3 x [8 x [4 x i16*]]], align 4

‎llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

Lines changed: 90 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -12,52 +12,51 @@ body: |
1212
bb.0:
1313
; CHECK-LABEL: name: func0
1414
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
15-
; CHECK-NEXT: {{ }}
16-
; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
17-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
18-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
19-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
20-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
21-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
22-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
23-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
24-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
25-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
26-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
27-
; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg
28-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 56
29-
; CHECK-NEXT: $r0 = IMPLICIT_DEF
30-
; CHECK-NEXT: $r1 = IMPLICIT_DEF
31-
; CHECK-NEXT: $r2 = IMPLICIT_DEF
32-
; CHECK-NEXT: $r3 = IMPLICIT_DEF
33-
; CHECK-NEXT: $r4 = IMPLICIT_DEF
34-
; CHECK-NEXT: $r5 = IMPLICIT_DEF
35-
; CHECK-NEXT: $r6 = IMPLICIT_DEF
36-
; CHECK-NEXT: $r7 = IMPLICIT_DEF
37-
; CHECK-NEXT: $r8 = IMPLICIT_DEF
38-
; CHECK-NEXT: $r9 = IMPLICIT_DEF
39-
; CHECK-NEXT: $r10 = IMPLICIT_DEF
40-
; CHECK-NEXT: $r11 = IMPLICIT_DEF
41-
; CHECK-NEXT: $r12 = IMPLICIT_DEF
42-
; CHECK-NEXT: $lr = IMPLICIT_DEF
43-
; CHECK-NEXT: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)
44-
; CHECK-NEXT: $r0 = tMOVr killed $sp, 14, $noreg
45-
; CHECK-NEXT: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
46-
; CHECK-NEXT: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)
47-
; CHECK-NEXT: KILL $r0
48-
; CHECK-NEXT: KILL $r1
49-
; CHECK-NEXT: KILL $r2
50-
; CHECK-NEXT: KILL $r3
51-
; CHECK-NEXT: KILL $r4
52-
; CHECK-NEXT: KILL $r5
53-
; CHECK-NEXT: KILL $r6
54-
; CHECK-NEXT: KILL $r7
55-
; CHECK-NEXT: KILL $r8
56-
; CHECK-NEXT: KILL $r9
57-
; CHECK-NEXT: KILL $r10
58-
; CHECK-NEXT: KILL $r11
59-
; CHECK-NEXT: KILL $r12
60-
; CHECK-NEXT: KILL $lr
15+
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
16+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
17+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
18+
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
19+
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
20+
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
21+
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
22+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
23+
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
24+
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
25+
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
26+
; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg
27+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56
28+
; CHECK: $r0 = IMPLICIT_DEF
29+
; CHECK: $r1 = IMPLICIT_DEF
30+
; CHECK: $r2 = IMPLICIT_DEF
31+
; CHECK: $r3 = IMPLICIT_DEF
32+
; CHECK: $r4 = IMPLICIT_DEF
33+
; CHECK: $r5 = IMPLICIT_DEF
34+
; CHECK: $r6 = IMPLICIT_DEF
35+
; CHECK: $r7 = IMPLICIT_DEF
36+
; CHECK: $r8 = IMPLICIT_DEF
37+
; CHECK: $r9 = IMPLICIT_DEF
38+
; CHECK: $r10 = IMPLICIT_DEF
39+
; CHECK: $r11 = IMPLICIT_DEF
40+
; CHECK: $r12 = IMPLICIT_DEF
41+
; CHECK: $lr = IMPLICIT_DEF
42+
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)
43+
; CHECK: $r0 = tMOVr killed $sp, 14, $noreg
44+
; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
45+
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)
46+
; CHECK: KILL $r0
47+
; CHECK: KILL $r1
48+
; CHECK: KILL $r2
49+
; CHECK: KILL $r3
50+
; CHECK: KILL $r4
51+
; CHECK: KILL $r5
52+
; CHECK: KILL $r6
53+
; CHECK: KILL $r7
54+
; CHECK: KILL $r8
55+
; CHECK: KILL $r9
56+
; CHECK: KILL $r10
57+
; CHECK: KILL $r11
58+
; CHECK: KILL $r12
59+
; CHECK: KILL $lr
6160
$r0 = IMPLICIT_DEF
6261
$r1 = IMPLICIT_DEF
6362
$r2 = IMPLICIT_DEF
@@ -106,52 +105,51 @@ body: |
106105
bb.0:
107106
; CHECK-LABEL: name: func1
108107
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
109-
; CHECK-NEXT: {{ }}
110-
; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
111-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
112-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
113-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
114-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
115-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
116-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
117-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
118-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
119-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
120-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
121-
; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg
122-
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
123-
; CHECK-NEXT: $r0 = IMPLICIT_DEF
124-
; CHECK-NEXT: $r1 = IMPLICIT_DEF
125-
; CHECK-NEXT: $r2 = IMPLICIT_DEF
126-
; CHECK-NEXT: $r3 = IMPLICIT_DEF
127-
; CHECK-NEXT: $r4 = IMPLICIT_DEF
128-
; CHECK-NEXT: $r5 = IMPLICIT_DEF
129-
; CHECK-NEXT: $r6 = IMPLICIT_DEF
130-
; CHECK-NEXT: $r7 = IMPLICIT_DEF
131-
; CHECK-NEXT: $r8 = IMPLICIT_DEF
132-
; CHECK-NEXT: $r9 = IMPLICIT_DEF
133-
; CHECK-NEXT: $r10 = IMPLICIT_DEF
134-
; CHECK-NEXT: $r11 = IMPLICIT_DEF
135-
; CHECK-NEXT: $r12 = IMPLICIT_DEF
136-
; CHECK-NEXT: $lr = IMPLICIT_DEF
137-
; CHECK-NEXT: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)
138-
; CHECK-NEXT: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg
139-
; CHECK-NEXT: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
140-
; CHECK-NEXT: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)
141-
; CHECK-NEXT: KILL $r0
142-
; CHECK-NEXT: KILL $r1
143-
; CHECK-NEXT: KILL $r2
144-
; CHECK-NEXT: KILL $r3
145-
; CHECK-NEXT: KILL $r4
146-
; CHECK-NEXT: KILL $r5
147-
; CHECK-NEXT: KILL $r6
148-
; CHECK-NEXT: KILL $r7
149-
; CHECK-NEXT: KILL $r8
150-
; CHECK-NEXT: KILL $r9
151-
; CHECK-NEXT: KILL $r10
152-
; CHECK-NEXT: KILL $r11
153-
; CHECK-NEXT: KILL $r12
154-
; CHECK-NEXT: KILL $lr
108+
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
109+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
110+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
111+
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
112+
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
113+
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
114+
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
115+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
116+
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
117+
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
118+
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
119+
; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg
120+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
121+
; CHECK: $r0 = IMPLICIT_DEF
122+
; CHECK: $r1 = IMPLICIT_DEF
123+
; CHECK: $r2 = IMPLICIT_DEF
124+
; CHECK: $r3 = IMPLICIT_DEF
125+
; CHECK: $r4 = IMPLICIT_DEF
126+
; CHECK: $r5 = IMPLICIT_DEF
127+
; CHECK: $r6 = IMPLICIT_DEF
128+
; CHECK: $r7 = IMPLICIT_DEF
129+
; CHECK: $r8 = IMPLICIT_DEF
130+
; CHECK: $r9 = IMPLICIT_DEF
131+
; CHECK: $r10 = IMPLICIT_DEF
132+
; CHECK: $r11 = IMPLICIT_DEF
133+
; CHECK: $r12 = IMPLICIT_DEF
134+
; CHECK: $lr = IMPLICIT_DEF
135+
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)
136+
; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg
137+
; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
138+
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)
139+
; CHECK: KILL $r0
140+
; CHECK: KILL $r1
141+
; CHECK: KILL $r2
142+
; CHECK: KILL $r3
143+
; CHECK: KILL $r4
144+
; CHECK: KILL $r5
145+
; CHECK: KILL $r6
146+
; CHECK: KILL $r7
147+
; CHECK: KILL $r8
148+
; CHECK: KILL $r9
149+
; CHECK: KILL $r10
150+
; CHECK: KILL $r11
151+
; CHECK: KILL $r12
152+
; CHECK: KILL $lr
155153
$r0 = IMPLICIT_DEF
156154
$r1 = IMPLICIT_DEF
157155
$r2 = IMPLICIT_DEF

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