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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360085 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/X86/X86InstrAVX512.td

Lines changed: 24 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -7191,7 +7191,8 @@ defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h,
71917191

71927192
multiclass avx512_vcvtsi<bits<8> opc, SDPatternOperator OpNode, X86FoldableSchedWrite sched,
71937193
RegisterClass SrcRC, X86VectorVTInfo DstVT,
7194-
X86MemOperand x86memop, PatFrag ld_frag, string asm> {
7194+
X86MemOperand x86memop, PatFrag ld_frag, string asm,
7195+
string mem> {
71957196
let hasSideEffects = 0, isCodeGenOnly = 1 in {
71967197
def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
71977198
(ins DstVT.FRC:$src1, SrcRC:$src),
@@ -7200,7 +7201,7 @@ multiclass avx512_vcvtsi<bits<8> opc, SDPatternOperator OpNode, X86FoldableSched
72007201
let mayLoad = 1 in
72017202
def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
72027203
(ins DstVT.FRC:$src1, x86memop:$src),
7203-
!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
7204+
asm#"{"#mem#"}\t{$src, $src1, $dst|$dst, $src1, $src}", []>,
72047205
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
72057206
} // hasSideEffects = 0
72067207
def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
@@ -7212,16 +7213,20 @@ multiclass avx512_vcvtsi<bits<8> opc, SDPatternOperator OpNode, X86FoldableSched
72127213

72137214
def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
72147215
(ins DstVT.RC:$src1, x86memop:$src2),
7215-
!strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7216+
asm#"{"#mem#"}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
72167217
[(set DstVT.RC:$dst,
72177218
(OpNode (DstVT.VT DstVT.RC:$src1),
72187219
(ld_frag addr:$src2)))]>,
72197220
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
7221+
def : InstAlias<"v"#asm#mem#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7222+
(!cast<Instruction>(NAME#"rr_Int") DstVT.RC:$dst,
7223+
DstVT.RC:$src1, SrcRC:$src2), 0, "att">;
72207224
}
72217225

72227226
multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode,
72237227
X86FoldableSchedWrite sched, RegisterClass SrcRC,
7224-
X86VectorVTInfo DstVT, string asm> {
7228+
X86VectorVTInfo DstVT, string asm,
7229+
string mem> {
72257230
def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
72267231
(ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
72277232
!strconcat(asm,
@@ -7231,32 +7236,36 @@ multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode,
72317236
SrcRC:$src2,
72327237
(i32 timm:$rc)))]>,
72337238
EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
7239+
def : InstAlias<"v"#asm#mem#"\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}",
7240+
(!cast<Instruction>(NAME#"rrb_Int") DstVT.RC:$dst,
7241+
DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc), 0, "att">;
72347242
}
72357243

72367244
multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, SDNode OpNodeRnd,
72377245
X86FoldableSchedWrite sched,
72387246
RegisterClass SrcRC, X86VectorVTInfo DstVT,
7239-
X86MemOperand x86memop, PatFrag ld_frag, string asm> {
7240-
defm NAME : avx512_vcvtsi_round<opc, OpNodeRnd, sched, SrcRC, DstVT, asm>,
7247+
X86MemOperand x86memop, PatFrag ld_frag,
7248+
string asm, string mem> {
7249+
defm NAME : avx512_vcvtsi_round<opc, OpNodeRnd, sched, SrcRC, DstVT, asm, mem>,
72417250
avx512_vcvtsi<opc, OpNode, sched, SrcRC, DstVT, x86memop,
7242-
ld_frag, asm>, VEX_LIG;
7251+
ld_frag, asm, mem>, VEX_LIG;
72437252
}
72447253

72457254
let Predicates = [HasAVX512] in {
72467255
defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd,
72477256
WriteCvtI2SS, GR32,
7248-
v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
7257+
v4f32x_info, i32mem, loadi32, "cvtsi2ss", "l">,
72497258
XS, EVEX_CD8<32, CD8VT1>;
72507259
defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd,
72517260
WriteCvtI2SS, GR64,
7252-
v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
7261+
v4f32x_info, i64mem, loadi64, "cvtsi2ss", "q">,
72537262
XS, VEX_W, EVEX_CD8<64, CD8VT1>;
72547263
defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, null_frag, WriteCvtI2SD, GR32,
7255-
v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
7264+
v2f64x_info, i32mem, loadi32, "cvtsi2sd", "l">,
72567265
XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
72577266
defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd,
72587267
WriteCvtI2SD, GR64,
7259-
v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
7268+
v2f64x_info, i64mem, loadi64, "cvtsi2sd", "q">,
72607269
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
72617270

72627271
def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
@@ -7285,17 +7294,17 @@ def : Pat<(f64 (sint_to_fp GR64:$src)),
72857294
defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd,
72867295
WriteCvtI2SS, GR32,
72877296
v4f32x_info, i32mem, loadi32,
7288-
"cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
7297+
"cvtusi2ss", "l">, XS, EVEX_CD8<32, CD8VT1>;
72897298
defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd,
72907299
WriteCvtI2SS, GR64,
7291-
v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
7300+
v4f32x_info, i64mem, loadi64, "cvtusi2ss", "q">,
72927301
XS, VEX_W, EVEX_CD8<64, CD8VT1>;
72937302
defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, null_frag, WriteCvtI2SD, GR32, v2f64x_info,
7294-
i32mem, loadi32, "cvtusi2sd{l}">,
7303+
i32mem, loadi32, "cvtusi2sd", "l">,
72957304
XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
72967305
defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd,
72977306
WriteCvtI2SD, GR64,
7298-
v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
7307+
v2f64x_info, i64mem, loadi64, "cvtusi2sd", "q">,
72997308
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
73007309

73017310
def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",

‎lib/Target/X86/X86InstrSSE.td

Lines changed: 56 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -822,14 +822,16 @@ let Constraints = "$src1 = $dst" in {
822822

823823
multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
824824
SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
825-
string asm, X86FoldableSchedWrite sched,
825+
string asm, string mem, X86FoldableSchedWrite sched,
826826
SchedRead Int2Fpu = ReadDefault> {
827-
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
828-
[(set DstRC:$dst, (OpNode SrcRC:$src))]>,
829-
Sched<[sched, Int2Fpu]>;
830-
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
831-
[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>,
832-
Sched<[sched.Folded]>;
827+
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
828+
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
829+
[(set DstRC:$dst, (OpNode SrcRC:$src))]>,
830+
Sched<[sched, Int2Fpu]>;
831+
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
832+
mem#"\t{$src, $dst|$dst, $src}",
833+
[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>,
834+
Sched<[sched.Folded]>;
833835
}
834836

835837
multiclass sse12_cvt_p<bits<8> opc, RegisterClass RC, X86MemOperand x86memop,
@@ -848,7 +850,7 @@ let hasSideEffects = 0 in {
848850
}
849851

850852
multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
851-
X86MemOperand x86memop, string asm,
853+
X86MemOperand x86memop, string asm, string mem,
852854
X86FoldableSchedWrite sched> {
853855
let hasSideEffects = 0, Predicates = [UseAVX] in {
854856
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
@@ -857,26 +859,26 @@ let hasSideEffects = 0, Predicates = [UseAVX] in {
857859
let mayLoad = 1 in
858860
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
859861
(ins DstRC:$src1, x86memop:$src),
860-
!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
862+
asm#"{"#mem#"}\t{$src, $src1, $dst|$dst, $src1, $src}", []>,
861863
Sched<[sched.Folded, sched.ReadAfterFold]>;
862864
} // hasSideEffects = 0
863865
}
864866

865867
let isCodeGenOnly = 1, Predicates = [UseAVX] in {
866868
defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
867-
"cvttss2si\t{$src, $dst|$dst, $src}",
869+
"cvttss2si", "cvttss2si",
868870
WriteCvtSS2I>,
869871
XS, VEX, VEX_LIG;
870872
defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
871-
"cvttss2si\t{$src, $dst|$dst, $src}",
873+
"cvttss2si", "cvttss2si",
872874
WriteCvtSS2I>,
873875
XS, VEX, VEX_W, VEX_LIG;
874876
defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
875-
"cvttsd2si\t{$src, $dst|$dst, $src}",
877+
"cvttsd2si", "cvttsd2si",
876878
WriteCvtSD2I>,
877879
XD, VEX, VEX_LIG;
878880
defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
879-
"cvttsd2si\t{$src, $dst|$dst, $src}",
881+
"cvttsd2si", "cvttsd2si",
880882
WriteCvtSD2I>,
881883
XD, VEX, VEX_W, VEX_LIG;
882884
}
@@ -886,13 +888,13 @@ defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
886888
// provide other assembly "l" and "q" forms to address this explicitly
887889
// where appropriate to do so.
888890
let isCodeGenOnly = 1 in {
889-
defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}",
891+
defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss", "l",
890892
WriteCvtI2SS>, XS, VEX_4V, VEX_LIG;
891-
defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}",
893+
defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss", "q",
892894
WriteCvtI2SS>, XS, VEX_4V, VEX_W, VEX_LIG;
893-
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}",
895+
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd", "l",
894896
WriteCvtI2SD>, XD, VEX_4V, VEX_LIG;
895-
defm VCVTSI642SD : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}",
897+
defm VCVTSI642SD : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd", "q",
896898
WriteCvtI2SD>, XD, VEX_4V, VEX_W, VEX_LIG;
897899
} // isCodeGenOnly = 1
898900

@@ -918,28 +920,28 @@ let Predicates = [UseAVX] in {
918920

919921
let isCodeGenOnly = 1 in {
920922
defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
921-
"cvttss2si\t{$src, $dst|$dst, $src}",
923+
"cvttss2si", "cvttss2si",
922924
WriteCvtSS2I>, XS;
923925
defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
924-
"cvttss2si\t{$src, $dst|$dst, $src}",
926+
"cvttss2si", "cvttss2si",
925927
WriteCvtSS2I>, XS, REX_W;
926928
defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
927-
"cvttsd2si\t{$src, $dst|$dst, $src}",
929+
"cvttsd2si", "cvttsd2si",
928930
WriteCvtSD2I>, XD;
929931
defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
930-
"cvttsd2si\t{$src, $dst|$dst, $src}",
932+
"cvttsd2si", "cvttsd2si",
931933
WriteCvtSD2I>, XD, REX_W;
932934
defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
933-
"cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
935+
"cvtsi2ss", "cvtsi2ss{l}",
934936
WriteCvtI2SS, ReadInt2Fpu>, XS;
935937
defm CVTSI642SS : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
936-
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
938+
"cvtsi2ss", "cvtsi2ss{q}",
937939
WriteCvtI2SS, ReadInt2Fpu>, XS, REX_W;
938940
defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
939-
"cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
941+
"cvtsi2sd", "cvtsi2sd{l}",
940942
WriteCvtI2SD, ReadInt2Fpu>, XD;
941943
defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
942-
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
944+
"cvtsi2sd", "cvtsi2sd{q}",
943945
WriteCvtI2SD, ReadInt2Fpu>, XD, REX_W;
944946
} // isCodeGenOnly = 1
945947

@@ -962,7 +964,7 @@ multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
962964

963965
multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
964966
RegisterClass DstRC, X86MemOperand x86memop,
965-
string asm, X86FoldableSchedWrite sched,
967+
string asm, string mem, X86FoldableSchedWrite sched,
966968
bit Is2Addr = 1> {
967969
let hasSideEffects = 0 in {
968970
def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
@@ -974,8 +976,8 @@ let hasSideEffects = 0 in {
974976
def rm_Int : SI<opc, MRMSrcMem, (outs DstRC:$dst),
975977
(ins DstRC:$src1, x86memop:$src2),
976978
!if(Is2Addr,
977-
!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
978-
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
979+
asm#"{"#mem#"}\t{$src2, $dst|$dst, $src2}",
980+
asm#"{"#mem#"}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
979981
[]>, Sched<[sched.Folded, sched.ReadAfterFold]>;
980982
}
981983
}
@@ -996,30 +998,48 @@ defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v2f64, X86cvts2si,
996998

997999
let Predicates = [UseAVX] in {
9981000
defm VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
999-
i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG;
1001+
i32mem, "cvtsi2ss", "l", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG;
10001002
defm VCVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1001-
i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG, VEX_W;
1003+
i64mem, "cvtsi2ss", "q", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_LIG, VEX_W;
10021004
defm VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1003-
i32mem, "cvtsi2sd{l}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG;
1005+
i32mem, "cvtsi2sd", "l", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG;
10041006
defm VCVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1005-
i64mem, "cvtsi2sd{q}", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG, VEX_W;
1007+
i64mem, "cvtsi2sd", "q", WriteCvtI2SD, 0>, XD, VEX_4V, VEX_LIG, VEX_W;
10061008
}
10071009
let Constraints = "$src1 = $dst" in {
10081010
defm CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1009-
i32mem, "cvtsi2ss{l}", WriteCvtI2SS>, XS;
1011+
i32mem, "cvtsi2ss", "l", WriteCvtI2SS>, XS;
10101012
defm CVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1011-
i64mem, "cvtsi2ss{q}", WriteCvtI2SS>, XS, REX_W;
1013+
i64mem, "cvtsi2ss", "q", WriteCvtI2SS>, XS, REX_W;
10121014
defm CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1013-
i32mem, "cvtsi2sd{l}", WriteCvtI2SD>, XD;
1015+
i32mem, "cvtsi2sd", "l", WriteCvtI2SD>, XD;
10141016
defm CVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1015-
i64mem, "cvtsi2sd{q}", WriteCvtI2SD>, XD, REX_W;
1017+
i64mem, "cvtsi2sd", "q", WriteCvtI2SD>, XD, REX_W;
10161018
}
10171019

1020+
def : InstAlias<"vcvtsi2ss{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1021+
(VCVTSI2SSrr_Int VR128:$dst, VR128:$src1, GR32:$src2), 0, "att">;
1022+
def : InstAlias<"vcvtsi2ss{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1023+
(VCVTSI642SSrr_Int VR128:$dst, VR128:$src1, GR64:$src2), 0, "att">;
1024+
def : InstAlias<"vcvtsi2sd{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1025+
(VCVTSI2SDrr_Int VR128:$dst, VR128:$src1, GR32:$src2), 0, "att">;
1026+
def : InstAlias<"vcvtsi2sd{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1027+
(VCVTSI642SDrr_Int VR128:$dst, VR128:$src1, GR64:$src2), 0, "att">;
1028+
10181029
def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
10191030
(VCVTSI2SSrm_Int VR128:$dst, VR128:$src1, i32mem:$src), 0, "att">;
10201031
def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
10211032
(VCVTSI2SDrm_Int VR128:$dst, VR128:$src1, i32mem:$src), 0, "att">;
10221033

1034+
def : InstAlias<"cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1035+
(CVTSI2SSrr_Int VR128:$dst, GR32:$src), 0, "att">;
1036+
def : InstAlias<"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1037+
(CVTSI642SSrr_Int VR128:$dst, GR64:$src), 0, "att">;
1038+
def : InstAlias<"cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1039+
(CVTSI2SDrr_Int VR128:$dst, GR32:$src), 0, "att">;
1040+
def : InstAlias<"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1041+
(CVTSI642SDrr_Int VR128:$dst, GR64:$src), 0, "att">;
1042+
10231043
def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
10241044
(CVTSI2SSrm_Int VR128:$dst, i32mem:$src), 0, "att">;
10251045
def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",

‎test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,13 @@ define %struct.__vv* @t(%struct.Key* %desc, i64 %p) nounwind ssp {
3939
; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
4040
; CHECK-NEXT: movl 0, %eax
4141
; CHECK-NEXT: xorps %xmm0, %xmm0
42-
; CHECK-NEXT: cvtsi2ssq %rax, %xmm0
42+
; CHECK-NEXT: cvtsi2ss %rax, %xmm0
4343
; CHECK-NEXT: movl 4, %eax
4444
; CHECK-NEXT: xorps %xmm1, %xmm1
45-
; CHECK-NEXT: cvtsi2ssq %rax, %xmm1
45+
; CHECK-NEXT: cvtsi2ss %rax, %xmm1
4646
; CHECK-NEXT: movl 8, %eax
4747
; CHECK-NEXT: xorps %xmm2, %xmm2
48-
; CHECK-NEXT: cvtsi2ssq %rax, %xmm2
48+
; CHECK-NEXT: cvtsi2ss %rax, %xmm2
4949
; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
5050
; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
5151
; CHECK-NEXT: movaps %xmm0, 0

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