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[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
GFX10 deprecates v_mul_lo_i32 instruction, so choose u32 form for all targets. Differential Revision: https://reviews.llvm.org/D61525 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360094 91177308-0d34-0410-b5e6-96231b3b80d8
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-100
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14 files changed

+142
-100
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‎lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3370,7 +3370,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
33703370
case AMDGPU::S_SUB_U32:
33713371
return AMDGPU::V_SUB_I32_e32;
33723372
case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
3373-
case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
3373+
case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_U32;
33743374
case AMDGPU::S_MUL_HI_U32: return AMDGPU::V_MUL_HI_U32;
33753375
case AMDGPU::S_MUL_HI_I32: return AMDGPU::V_MUL_HI_I32;
33763376
case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;

‎test/CodeGen/AMDGPU/add3.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -131,13 +131,13 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
131131
; VI: ; %bb.0:
132132
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
133133
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
134-
; VI-NEXT: v_mul_lo_i32 v1, v0, v3
134+
; VI-NEXT: v_mul_lo_u32 v1, v0, v3
135135
; VI-NEXT: ; return to shader part epilog
136136
;
137137
; GFX9-LABEL: add3_multiuse_outer:
138138
; GFX9: ; %bb.0:
139139
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
140-
; GFX9-NEXT: v_mul_lo_i32 v1, v0, v3
140+
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
141141
; GFX9-NEXT: ; return to shader part epilog
142142
%inner = add i32 %a, %b
143143
%outer = add i32 %inner, %c

‎test/CodeGen/AMDGPU/frame-index-elimination.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ define void @func_add_constant_to_fi_i32() #0 {
6060
; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
6161
; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
6262

63-
; GCN-NEXT: v_mul_lo_i32 v0, v0, 9
63+
; GCN-NEXT: v_mul_lo_u32 v0, v0, 9
6464
; GCN-NOT: v_mov
6565
; GCN: ds_write_b32 v0, v0
6666
define void @func_other_fi_user_i32() #0 {
@@ -172,7 +172,7 @@ ret:
172172
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
173173
; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], s6, [[SCALED]]
174174

175-
; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
175+
; GCN: v_mul_lo_u32 [[VZ]], [[VZ]], 9
176176
; GCN: ds_write_b32 v0, [[VZ]]
177177
define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
178178
%alloca0 = alloca [128 x i32], align 4, addrspace(5)
@@ -196,7 +196,7 @@ define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
196196
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
197197
; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], [[OFFSET]], [[SCALED]]
198198

199-
; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
199+
; GCN: v_mul_lo_u32 [[VZ]], [[VZ]], 9
200200
; GCN: ds_write_b32 v0, [[VZ]]
201201
define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
202202
%alloca0 = alloca [128 x i32], align 4, addrspace(5)

‎test/CodeGen/AMDGPU/idiv-licm.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x4f800000,
77
; GCN: v_cvt_u32_f32_e32
88
; GCN-DAG: v_mul_hi_u32
9-
; GCN-DAG: v_mul_lo_i32
9+
; GCN-DAG: v_mul_lo_u32
1010
; GCN-DAG: v_sub_i32_e32
1111
; GCN-DAG: v_cmp_eq_u32_e64
1212
; GCN-DAG: v_cndmask_b32_e64
@@ -42,7 +42,7 @@ bb3: ; preds = %bb3, %bb
4242
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x4f800000,
4343
; GCN: v_cvt_u32_f32_e32
4444
; GCN-DAG: v_mul_hi_u32
45-
; GCN-DAG: v_mul_lo_i32
45+
; GCN-DAG: v_mul_lo_u32
4646
; GCN-DAG: v_sub_i32_e32
4747
; GCN-DAG: v_cmp_eq_u32_e64
4848
; GCN-DAG: v_cndmask_b32_e64
@@ -78,7 +78,7 @@ bb3: ; preds = %bb3, %bb
7878
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x4f800000,
7979
; GCN: v_cvt_u32_f32_e32
8080
; GCN-DAG: v_mul_hi_u32
81-
; GCN-DAG: v_mul_lo_i32
81+
; GCN-DAG: v_mul_lo_u32
8282
; GCN-DAG: v_sub_i32_e32
8383
; GCN-DAG: v_cmp_eq_u32_e64
8484
; GCN-DAG: v_cndmask_b32_e64
@@ -114,7 +114,7 @@ bb3: ; preds = %bb3, %bb
114114
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x4f800000,
115115
; GCN: v_cvt_u32_f32_e32
116116
; GCN-DAG: v_mul_hi_u32
117-
; GCN-DAG: v_mul_lo_i32
117+
; GCN-DAG: v_mul_lo_u32
118118
; GCN-DAG: v_sub_i32_e32
119119
; GCN-DAG: v_cmp_eq_u32_e64
120120
; GCN-DAG: v_cndmask_b32_e64

‎test/CodeGen/AMDGPU/mad_64_32.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; GCN-LABEL: {{^}}mad_i64_i32_sextops:
55
; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
66

7-
; SI: v_mul_lo_i32
7+
; SI: v_mul_lo_u32
88
; SI: v_mul_hi_i32
99
; SI: v_add_i32
1010
; SI: v_addc_u32
@@ -19,7 +19,7 @@ define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
1919
; GCN-LABEL: {{^}}mad_i64_i32_sextops_commute:
2020
; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
2121

22-
; SI-DAG: v_mul_lo_i32
22+
; SI-DAG: v_mul_lo_u32
2323
; SI-DAG: v_mul_hi_i32
2424
; SI: v_add_i32
2525
; SI: v_addc_u32
@@ -34,7 +34,7 @@ define i64 @mad_i64_i32_sextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
3434
; GCN-LABEL: {{^}}mad_u64_u32_zextops:
3535
; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
3636

37-
; SI-DAG: v_mul_lo_i32
37+
; SI-DAG: v_mul_lo_u32
3838
; SI-DAG: v_mul_hi_u32
3939
; SI: v_add_i32
4040
; SI: v_addc_u32
@@ -49,7 +49,7 @@ define i64 @mad_u64_u32_zextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
4949
; GCN-LABEL: {{^}}mad_u64_u32_zextops_commute:
5050
; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
5151

52-
; SI-DAG: v_mul_lo_i32
52+
; SI-DAG: v_mul_lo_u32
5353
; SI-DAG: v_mul_hi_u32
5454
; SI: v_add_i32
5555
; SI: v_addc_u32

‎test/CodeGen/AMDGPU/mul.i16.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ define amdgpu_kernel void @s_mul_i16(i16 %a, i16 %b) {
2727
; FIXME: Should emit u16 mul here. Instead it's worse than SI
2828
; GCN-LABEL: {{^}}v_mul_i16_uniform_load:
2929
; SI: v_mul_u32_u24
30-
; GFX89: v_mul_lo_i32
30+
; GFX89: v_mul_lo_u32
3131
define amdgpu_kernel void @v_mul_i16_uniform_load(
3232
i16 addrspace(1)* %r,
3333
i16 addrspace(1)* %a,
@@ -41,8 +41,8 @@ entry:
4141
}
4242

4343
; GCN-LABEL: {{^}}v_mul_v2i16:
44-
; SI: v_mul_lo_i32
45-
; SI: v_mul_lo_i32
44+
; SI: v_mul_lo_u32
45+
; SI: v_mul_lo_u32
4646

4747
; VI: v_mul_lo_u16_sdwa
4848
; VI: v_mul_lo_u16_e32
@@ -59,9 +59,9 @@ define <2 x i16> @v_mul_v2i16(<2 x i16> %a, <2 x i16> %b) {
5959

6060
; FIXME: Unpack garbage on gfx9
6161
; GCN-LABEL: {{^}}v_mul_v3i16:
62-
; SI: v_mul_lo_i32
63-
; SI: v_mul_lo_i32
64-
; SI: v_mul_lo_i32
62+
; SI: v_mul_lo_u32
63+
; SI: v_mul_lo_u32
64+
; SI: v_mul_lo_u32
6565

6666
; VI: v_mul_lo_u16
6767
; VI: v_mul_lo_u16
@@ -77,10 +77,10 @@ define <3 x i16> @v_mul_v3i16(<3 x i16> %a, <3 x i16> %b) {
7777
}
7878

7979
; GCN-LABEL: {{^}}v_mul_v4i16:
80-
; SI: v_mul_lo_i32
81-
; SI: v_mul_lo_i32
82-
; SI: v_mul_lo_i32
83-
; SI: v_mul_lo_i32
80+
; SI: v_mul_lo_u32
81+
; SI: v_mul_lo_u32
82+
; SI: v_mul_lo_u32
83+
; SI: v_mul_lo_u32
8484

8585
; VI: v_mul_lo_u16_sdwa
8686
; VI: v_mul_lo_u16_e32

‎test/CodeGen/AMDGPU/mul.ll

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SI,FUNC %s
22
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,VI,FUNC %s
3-
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=FUNC,GFX9 %s
3+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=FUNC,GFX9_10 %s
4+
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=FUNC,GFX9_10 %s
45
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=EG,FUNC %s
56

67
; mul24 and mad24 are affected
@@ -9,8 +10,8 @@
910
; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
1011
; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
1112

12-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
13-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
13+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
14+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
1415

1516
define amdgpu_kernel void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
1617
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
@@ -27,10 +28,10 @@ define amdgpu_kernel void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32
2728
; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2829
; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
2930

30-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
33-
; GCN: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
33+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
34+
; GCN: v_mul_lo_u32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
3435

3536
define amdgpu_kernel void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
3637
%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
@@ -56,7 +57,7 @@ define amdgpu_kernel void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a
5657
; FUNC-LABEL: {{^}}v_trunc_i64_mul_to_i32:
5758
; GCN: s_load_dword
5859
; GCN: s_load_dword
59-
; GCN: v_mul_lo_i32
60+
; GCN: v_mul_lo_u32
6061
; GCN: buffer_store_dword
6162
define amdgpu_kernel void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
6263
%a = load i64, i64 addrspace(1)* %aptr, align 8
@@ -85,7 +86,7 @@ entry:
8586
; FUNC-LABEL: {{^}}v_mul64_sext_c:
8687
; EG-DAG: MULLO_INT
8788
; EG-DAG: MULHI_INT
88-
; GCN-DAG: v_mul_lo_i32
89+
; GCN-DAG: v_mul_lo_u32
8990
; GCN-DAG: v_mul_hi_i32
9091
; GCN: s_endpgm
9192
define amdgpu_kernel void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
@@ -97,7 +98,7 @@ define amdgpu_kernel void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(
9798
}
9899

99100
; FUNC-LABEL: {{^}}v_mul64_sext_inline_imm:
100-
; GCN-DAG: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
101+
; GCN-DAG: v_mul_lo_u32 v{{[0-9]+}}, v{{[0-9]+}}, 9
101102
; GCN-DAG: v_mul_hi_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
102103
; GCN: s_endpgm
103104
define amdgpu_kernel void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
@@ -122,7 +123,7 @@ define amdgpu_kernel void @s_mul_i32(i32 addrspace(1)* %out, [8 x i32], i32 %a,
122123
}
123124

124125
; FUNC-LABEL: {{^}}v_mul_i32:
125-
; GCN: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
126+
; GCN: v_mul_lo_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
126127
define amdgpu_kernel void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
127128
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
128129
%a = load i32, i32 addrspace(1)* %in
@@ -140,19 +141,19 @@ define amdgpu_kernel void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %
140141
; crash with a 'failed to select' error.
141142

142143
; FUNC-LABEL: {{^}}s_mul_i64:
143-
; GFX9-DAG: s_mul_i32
144-
; GFX9-DAG: s_mul_hi_u32
145-
; GFX9-DAG: s_mul_i32
146-
; GFX9-DAG: s_mul_i32
147-
; GFX9: s_endpgm
144+
; GFX9_10-DAG: s_mul_i32
145+
; GFX9_10-DAG: s_mul_hi_u32
146+
; GFX9_10-DAG: s_mul_i32
147+
; GFX9_10-DAG: s_mul_i32
148+
; GFX9_10: s_endpgm
148149
define amdgpu_kernel void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
149150
%mul = mul i64 %a, %b
150151
store i64 %mul, i64 addrspace(1)* %out, align 8
151152
ret void
152153
}
153154

154155
; FUNC-LABEL: {{^}}v_mul_i64:
155-
; GCN: v_mul_lo_i32
156+
; GCN: v_mul_lo_u32
156157
define amdgpu_kernel void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
157158
%a = load i64, i64 addrspace(1)* %aptr, align 8
158159
%b = load i64, i64 addrspace(1)* %bptr, align 8
@@ -250,26 +251,26 @@ define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, [8 x i32], i128 %
250251
; GCN: {{buffer|flat}}_load_dwordx4
251252
; GCN: {{buffer|flat}}_load_dwordx4
252253

253-
; SI-DAG: v_mul_lo_i32
254+
; SI-DAG: v_mul_lo_u32
254255
; SI-DAG: v_mul_hi_u32
255256
; SI-DAG: v_mul_hi_u32
256-
; SI-DAG: v_mul_lo_i32
257+
; SI-DAG: v_mul_lo_u32
257258
; SI-DAG: v_mul_hi_u32
258259
; SI-DAG: v_mul_hi_u32
259-
; SI-DAG: v_mul_lo_i32
260-
; SI-DAG: v_mul_lo_i32
260+
; SI-DAG: v_mul_lo_u32
261+
; SI-DAG: v_mul_lo_u32
261262
; SI-DAG: v_add_i32_e32
262263

263264
; SI-DAG: v_mul_hi_u32
264-
; SI-DAG: v_mul_lo_i32
265+
; SI-DAG: v_mul_lo_u32
265266
; SI-DAG: v_mul_hi_u32
266-
; SI-DAG: v_mul_lo_i32
267-
; SI-DAG: v_mul_lo_i32
268-
; SI-DAG: v_mul_lo_i32
269-
; SI-DAG: v_mul_lo_i32
270-
; SI-DAG: v_mul_lo_i32
267+
; SI-DAG: v_mul_lo_u32
268+
; SI-DAG: v_mul_lo_u32
269+
; SI-DAG: v_mul_lo_u32
270+
; SI-DAG: v_mul_lo_u32
271+
; SI-DAG: v_mul_lo_u32
271272

272-
; VI-DAG: v_mul_lo_i32
273+
; VI-DAG: v_mul_lo_u32
273274
; VI-DAG: v_mul_hi_u32
274275
; VI: v_mad_u64_u32
275276
; VI: v_mad_u64_u32

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