Description

The current implementation of adder_tree.sv contains a potential ​​compile-time index out-of-bounds error​​ due to unsafe always_comb logic inside the generate block. When INPUTS_NUM is not a power of two (e.g., 125), the generate loop may attempt to access idata[adder] with adder >= INPUTS_NUM , even if the else branch is logically unreachable.
This violates SystemVerilog's requirement that ​​constant indices must be compile-time valid​​, regardless of runtime conditions.

Current Problematic Code

always_comb begin
    if (adder < INPUTS_NUM) begin
        data[stage][adder][ST_WIDTH-1:0] <= idata[adder][ST_WIDTH-1:0]; // May OOB if adder >= INPUTS_NUM
        data[stage][adder][ODATA_WIDTH-1:ST_WIDTH] <= '0;
    end else begin
        data[stage][adder][ODATA_WIDTH-1:0] <= '0;
    end
end

Proposed Fix

if (adder < INPUTS_NUM) begin
    always_comb begin
        data[stage][adder][ST_WIDTH-1:0] <= idata[adder][ST_WIDTH-1:0];
        // Safe: only generated if adder < INPUTS_NUM
        data[stage][adder][ODATA_WIDTH-1:ST_WIDTH] <= '0;
    end
end else begin
    always_comb begin
        data[stage][adder][ODATA_WIDTH-1:0] <= '0;
    end
end

Impact

• ​​No functional change​​: The logic remains identical.
• ​Compilation safety​​: Eliminates "constant index out of bounds" errors.