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[RISCV] Add short forward branch scheduling for Andes45 #147890

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Merged
merged 1 commit into from
Jul 14, 2025

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tclin914
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@llvmbot
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llvmbot commented Jul 10, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/147890.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVSchedAndes45.td (+8-1)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index bd480aacc539e..214fd8158a679 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -54,6 +54,12 @@ def : WriteRes<WriteShiftImm32, [Andes45ALU]>;
 def : WriteRes<WriteShiftReg, [Andes45ALU]>;
 def : WriteRes<WriteShiftReg32, [Andes45ALU]>;
 
+// Short forward branch
+def : WriteRes<WriteSFB, [Andes45ALU]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+}
+
 // Branching
 def : WriteRes<WriteJmp, [Andes45ALU]>;
 def : WriteRes<WriteJal, [Andes45ALU]>;
@@ -231,6 +237,8 @@ def : ReadAdvance<ReadShiftImm, 0>;
 def : ReadAdvance<ReadShiftImm32, 0>;
 def : ReadAdvance<ReadShiftReg, 0>;
 def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadSFBJmp, 0>;
+def : ReadAdvance<ReadSFBALU, 0>;
 def : ReadAdvance<ReadJalr, 0>;
 def : ReadAdvance<ReadJmp, 0>;
 def : ReadAdvance<ReadIMul, 0>;
@@ -328,7 +336,6 @@ def : ReadAdvance<ReadCSR, 0>;
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedQ;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;

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LGTM

@mshockwave
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could you also add a simple MCA test if that's not a lot of work?

@tclin914
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could you also add a simple MCA test if that's not a lot of work?

I don't know how to add an MCA test to verify the scheduling info used by pseudo instructions (PseudoCC* in this case) :(

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could you also add a simple MCA test if that's not a lot of work?

I don't know how to add an MCA test to verify the scheduling info used by pseudo instructions (PseudoCC* in this case) :(

Oops you're right, nvm then

@tclin914 tclin914 merged commit 2886d30 into llvm:main Jul 14, 2025
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@tclin914 tclin914 deleted the andes45-sched-sfb branch July 14, 2025 01:26
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4 participants