Event timestamps are all recorded for compile-time CPU frequency, the timer ticks conversion

dok-net · dok-net · commit 5cabb91f8964 · 2020-05-11T10:20:15.000+02:00
must be set at compile-time also. The SDK WiFi 160MHz boost mitigation temporarily handles
the CPU clock running twice as fast.
diff --git a/cores/esp8266/core_esp8266_waveform.cpp b/cores/esp8266/core_esp8266_waveform.cpp
@@ -452,8 +452,9 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
   }
 
   // Register access is fast and edge IRQ was configured before.
-  // Timer is 80MHz fixed. 160MHz binaries need scaling,
-  // 80MHz binaries in 160MHz boost (SDK) need NMI scaling
-  // to maintain duty/idle ratio.
-  T1L = CPU2X & 1 ? nextTimerCcys >> 1 : nextTimerCcys;
+  // Timer is 80MHz fixed. 160MHz binaries need scaling.
+  // For dynamic CPU clock frequency switch in loop the scaling logic would have to be adapted.
+  // Using constexpr makes sure that the CPU clock frequency is compile-time fixed.
+  constexpr bool cpuFreq80MHz = clockCyclesPerMicrosecond() == 80;
+  T1L = cpuFreq80MHz ? nextTimerCcys : nextTimerCcys >> 1;
 }

Original file line number	Diff line number	Diff line change
`@@ -452,8 +452,9 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {`
`452`	`452`	`}`
`453`	`453`
`454`	`454`	`// Register access is fast and edge IRQ was configured before.`
`455`		`- // Timer is 80MHz fixed. 160MHz binaries need scaling,`
`456`		`- // 80MHz binaries in 160MHz boost (SDK) need NMI scaling`
`457`		`- // to maintain duty/idle ratio.`
`458`		`- T1L = CPU2X & 1 ? nextTimerCcys >> 1 : nextTimerCcys;`
	`455`	`+ // Timer is 80MHz fixed. 160MHz binaries need scaling.`
	`456`	`+ // For dynamic CPU clock frequency switch in loop the scaling logic would have to be adapted.`
	`457`	`+ // Using constexpr makes sure that the CPU clock frequency is compile-time fixed.`
	`458`	`+ constexpr bool cpuFreq80MHz = clockCyclesPerMicrosecond() == 80;`
	`459`	`+ T1L = cpuFreq80MHz ? nextTimerCcys : nextTimerCcys >> 1;`
`459`	`460`	`}`