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irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
1 parent aec0095 commit c011470

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17 files changed

+21
-131
lines changed

17 files changed

+21
-131
lines changed

arch/arm/mach-exynos/platsmp.c

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@@ -20,7 +20,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
23-
#include <linux/irqchip/arm-gic.h>
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2524
#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
@@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock);
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7675
static void __cpuinit exynos_secondary_init(unsigned int cpu)
7776
{
78-
/*
79-
* if any interrupts are already enabled for the primary
80-
* core (e.g. timer irq), then they will not have been enabled
81-
* for us: do so
82-
*/
83-
gic_secondary_init(0);
84-
8577
/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point

arch/arm/mach-highbank/platsmp.c

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@@ -17,19 +17,13 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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2221
#include <asm/smp_scu.h>
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#include "core.h"
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2625
extern void secondary_startup(void);
2726

28-
static void __cpuinit highbank_secondary_init(unsigned int cpu)
29-
{
30-
gic_secondary_init(0);
31-
}
32-
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static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
3428
{
3529
highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations highbank_smp_ops __initdata = {
6862
.smp_init_cpus = highbank_smp_init_cpus,
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.smp_prepare_cpus = highbank_smp_prepare_cpus,
70-
.smp_secondary_init = highbank_secondary_init,
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.smp_boot_secondary = highbank_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = highbank_cpu_die,

arch/arm/mach-imx/platsmp.c

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Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
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#include <linux/init.h>
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#include <linux/smp.h>
15-
#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
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writel_relaxed(val, scu_base);
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}
5453

55-
static void __cpuinit imx_secondary_init(unsigned int cpu)
56-
{
57-
/*
58-
* if any interrupts are already enabled for the primary
59-
* core (e.g. timer irq), then they will not have been enabled
60-
* for us: do so
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*/
62-
gic_secondary_init(0);
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}
64-
6554
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
6655
{
6756
imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations imx_smp_ops __initdata = {
9786
.smp_init_cpus = imx_smp_init_cpus,
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.smp_prepare_cpus = imx_smp_prepare_cpus,
99-
.smp_secondary_init = imx_secondary_init,
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.smp_boot_secondary = imx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = imx_cpu_die,

arch/arm/mach-msm/platsmp.c

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@@ -15,7 +15,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
1918

2019
#include <asm/cacheflush.h>
2120
#include <asm/cputype.h>
@@ -41,13 +40,6 @@ static inline int get_core_count(void)
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4241
static void __cpuinit msm_secondary_init(unsigned int cpu)
4342
{
44-
/*
45-
* if any interrupts are already enabled for the primary
46-
* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
49-
gic_secondary_init(0);
50-
5143
/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point

arch/arm/mach-omap2/omap-smp.c

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Original file line numberDiff line numberDiff line change
@@ -66,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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69-
/*
70-
* If any interrupts are already enabled for the primary
71-
* core (e.g. timer irq), then they will not have been enabled
72-
* for us: do so
73-
*/
74-
gic_secondary_init(0);
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7669
/*
7770
* Synchronise with the boot thread.
7871
*/

arch/arm/mach-prima2/platsmp.c

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@@ -11,7 +11,6 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
@@ -48,13 +47,6 @@ void __init sirfsoc_map_scu(void)
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static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
5049
{
51-
/*
52-
* if any interrupts are already enabled for the primary
53-
* core (e.g. timer irq), then they will not have been enabled
54-
* for us: do so
55-
*/
56-
gic_secondary_init(0);
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/*
5951
* let the primary processor know we're out of the
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* pen, then head off into the C entry point

arch/arm/mach-shmobile/smp-emev2.c

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@@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/emev2.h>
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#include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
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}
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88-
static void __cpuinit emev2_secondary_init(unsigned int cpu)
89-
{
90-
gic_secondary_init(0);
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}
92-
9387
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
9488
{
9589
cpu = cpu_logical_map(cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
124118
struct smp_operations emev2_smp_ops __initdata = {
125119
.smp_init_cpus = emev2_smp_init_cpus,
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.smp_prepare_cpus = emev2_smp_prepare_cpus,
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.smp_secondary_init = emev2_secondary_init,
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.smp_boot_secondary = emev2_boot_secondary,
129122
#ifdef CONFIG_HOTPLUG_CPU
130123
.cpu_kill = emev2_cpu_kill,

arch/arm/mach-shmobile/smp-r8a7779.c

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@@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
2424
#include <linux/io.h>
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#include <linux/delay.h>
26-
#include <linux/irqchip/arm-gic.h>
2726
#include <mach/common.h>
2827
#include <mach/r8a7779.h>
2928
#include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
132131
}
133132

134133

135-
static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
136-
{
137-
gic_secondary_init(0);
138-
}
139-
140134
static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
141135
{
142136
struct r8a7779_pm_ch *ch = NULL;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
186180
struct smp_operations r8a7779_smp_ops __initdata = {
187181
.smp_init_cpus = r8a7779_smp_init_cpus,
188182
.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
189-
.smp_secondary_init = r8a7779_secondary_init,
190183
.smp_boot_secondary = r8a7779_boot_secondary,
191184
#ifdef CONFIG_HOTPLUG_CPU
192185
.cpu_kill = r8a7779_cpu_kill,

arch/arm/mach-shmobile/smp-sh73a0.c

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@@ -23,7 +23,6 @@
2323
#include <linux/spinlock.h>
2424
#include <linux/io.h>
2525
#include <linux/delay.h>
26-
#include <linux/irqchip/arm-gic.h>
2726
#include <mach/common.h>
2827
#include <asm/cacheflush.h>
2928
#include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
5958
return scu_get_core_count(scu_base);
6059
}
6160

62-
static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
63-
{
64-
gic_secondary_init(0);
65-
}
66-
6761
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
6862
{
6963
cpu = cpu_logical_map(cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
138132
struct smp_operations sh73a0_smp_ops __initdata = {
139133
.smp_init_cpus = sh73a0_smp_init_cpus,
140134
.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
141-
.smp_secondary_init = sh73a0_secondary_init,
142135
.smp_boot_secondary = sh73a0_boot_secondary,
143136
#ifdef CONFIG_HOTPLUG_CPU
144137
.cpu_kill = sh73a0_cpu_kill,

arch/arm/mach-socfpga/platsmp.c

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@@ -22,7 +22,6 @@
2222
#include <linux/io.h>
2323
#include <linux/of.h>
2424
#include <linux/of_address.h>
25-
#include <linux/irqchip/arm-gic.h>
2625

2726
#include <asm/cacheflush.h>
2827
#include <asm/smp_scu.h>
@@ -33,16 +32,6 @@
3332
extern void __iomem *sys_manager_base_addr;
3433
extern void __iomem *rst_manager_base_addr;
3534

36-
static void __cpuinit socfpga_secondary_init(unsigned int cpu)
37-
{
38-
/*
39-
* if any interrupts are already enabled for the primary
40-
* core (e.g. timer irq), then they will not have been enabled
41-
* for us: do so
42-
*/
43-
gic_secondary_init(0);
44-
}
45-
4635
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
4736
{
4837
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu)
10998
struct smp_operations socfpga_smp_ops __initdata = {
11099
.smp_init_cpus = socfpga_smp_init_cpus,
111100
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
112-
.smp_secondary_init = socfpga_secondary_init,
113101
.smp_boot_secondary = socfpga_boot_secondary,
114102
#ifdef CONFIG_HOTPLUG_CPU
115103
.cpu_die = socfpga_cpu_die,

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